A dual-mode Q-enhanced RF front-end filter for 5 GHz WLAN and UWB with NB interference rejection

The 5 GHz Wireless LAN (802.11a) is a popular standard for wireless indoor communications providing moderate range and speed. Combined with the emerging ultra Wideband standard (UWB) for short range and high speed communications, the two standards promise to fulfil all areas of wireless application needs. However, due to the overlapping of the two spectrums, the stronger 802.11a signals tend to interfere causing degradation to the UWB receiver. This presents one of the main technical challenges preventing the wide acceptance of UWB. The research work presented in this thesis is to propose a low cost RF receiver front-end filter topology that would resolve the narrowband (NB) interference to UWB receiver while being operable in both 802.11a mode and UWB mode. The goal of the dual mode filter design is to reduce cost and complexity by developing a fully integrated front-end filter. The filter design utilizes high Q passive devices and Q-enhancement technique to provide front-end channel-selection in NB mode and NB interference rejection in UWB mode. In the 802.11a NB mode, the filter has a tunable gain of 4 dB to 25 dB, NF of 8 dB and an IIP3 between -47 dBm and -18 dBm. The input impedance is matched at -16 dB. The frequency of operation can be tuned from 5.15 GHz to 5.35 GHz. In the UWB mode, the filter has a gain of 0 dB to 8 dB across 3.1 GHz to 9 GHz. The filter can reject the NB interference between 5.15 GHz to 5.35 GHz at up to 60 dB. The Q of the filter is tunable up to a 250 while consuming a maximum of 23.4 mW of power. The fully integrated dual mode filter occupies a die area of 1.1 mm2

Parallel integrated receivers for multiple antenna wireless LAN systems

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 147-154).This thesis focuses on the design of power- and area-efficient parallel integrated receivers for multiple antenna wireless LAN systems. These receivers are part of an indoor parallel radio system that achieves 1 gigabit per second data rates and enables high bandwidth wireless communication between portable user devices and a high speed wired internet connection. Since a critical aspect for efficiency is that an optimal number of transceivers be used to meet system requirements, this thesis first considers power dissipation and area. consumption for parallel integrated transceivers. It develops parallel transceiver power dissipation and area consumption models that are functions of distance, data rate, and noise figure and incorporate the behavior of a multiple-input, multiple-output channel and power dissipation and area consumption values for typical RF circuits. These models properly balance benefits of multiple antennas with drawbacks due to parallel radio overhead. Their application shows that the combined transceiver power dissipation can actually decrease with more antennas and also provides a circuits-based number of antennas upper bound that has not been established previously.(cont.) The thesis then proposes a solution that applies multiple antenna signal-to-noise ratio (SNR) gain at the receiver to reduce its power dissipation and area consumption. SNR gain trades noise figure for power- and area-efficient circuits. The implementation of a, single chip 5.22-GHz area-efficient parallel receiver RFIC that shows practical application of these models, SNR gain, and area-efficient circuits is demonstrated. The context of this design comes from the Wireless Gigabit Local Area Network (WiGLAN). It's system characteristics such as a wide 150 MHz bandwidth and parallel radios uniquely determine a WiGLAN parallel receiver design.by Lunal Khuon.Ph.D

High performance continuous-time filters for information transfer systems

Vast attention has been paid to active continuous-time filters over the years. Thus as the cheap, readily available integrated circuit OpAmps replaced their discrete circuit versions, it became feasible to consider active-RC filter circuits using large numbers of OpAmps. Similarly the development of integrated operational transconductance amplifier (OTA) led to new filter configurations. This gave rise to OTA-C filters, using only active devices and capacitors, making it more suitable for integration. The demands on filter circuits have become ever more stringent as the world of electronics and communications has advanced. In addition, the continuing increase in the operating frequencies of modern circuits and systems increases the need for active filters that can perform at these higher frequencies; an area where the LC active filter emerges. What mainly limits the performance of an analog circuit are the non-idealities of the used building blocks and the circuit architecture. This research concentrates on the design issues of high frequency continuous-time integrated filters. Several novel circuit building blocks are introduced. A novel pseudo-differential fully balanced fully symmetric CMOS OTA architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. On the level of system architectures, a novel filter low-voltage 4th order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled-inductors, thus providing bandwidth tuning with small passband ripple. As part of a direct conversion dual-mode 802.11b/Bluetooth receiver, a BiCMOS 5th order low-pass channel selection filter is designed. The filter operated from a single 2.5V supply and achieves a 76dB of out-of-band SFDR. A digital automatic tuning system is also implemented to account for process and temperature variations. As part of a Bluetooth transmitter, a low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications

Solutions for image rejection CMOS LNA

This paper deals with the realization of a high image rejection (IR) CMOS LNA, tailored to DECT applications. Two topologies are proposed. The first one makes use of a Q-enhancement circuit and provides 15 dB IR with 300 MHz IF, 4.5 dB NF and -13 dBm IIP3. A notch filter loads the second LNA. The results are the following: 30 dB IR, 5.5 dB NF and -10 dBm IIP3. In both cases the frequency control is performed by means of an integrated MOS varactor. These circuits prove to be suitable for highly integrated CMOS receivers employing wideband IF architecture. At the expense of an almost double current consumption with respect to classical LNA, they provide enough image rejection to get rid of off-chip image rejection filter