Variability analysis of FinFET AC/RF performances through efficient physics-based simulations for the optimization of RF CMOS stages

A nearly insatiable appetite for the latest electronic device enables the electronic technology sector to maintain research momentum. The necessity for advancement with miniaturization of electronic devices is the need of the day. Aggressive downscaling of electronic devices face some fundamental limits and thus, buoy up the change in device geometry. MOSFETs have been the leading contender in the electronics industry for years, but the dire need for miniaturization is forcing MOSFET to be scaled to nano-scale and in sub-50 nm scale. Short channel effects (SCE) become dominant and adversely affect the performance of the MOSFET. So, the need for a novel structure was felt to suppress SCE to an acceptable level. Among the proposed devices, FinFETs (Fin Field Effect Transistors) were found to be most effective to counter-act SCE in electronic devices. Today, many industries are working on electronic circuits with FinFETs as their primary element.One of limitation which FinFET faces is device variability. The purpose of this work was to study the effect that different sources of parameter fluctuations have on the behavior and characteristics of FinFETs. With deep literature review, we have gained insight into key sources of variability. Different sources of variations, like random dopant fluctuation, line edge roughness, fin variations, workfunction variations, oxide thickness variation, and source/drain doping variations, were studied and their impact on the performance of the device was studied as well. The adverse effect of these variations fosters the great amount of research towards variability modeling. A proper modeling of these variations is required to address the device performance metric before the fabrication of any new generation of the device on the commercial scale. The conventional methods to address the characteristics of a device under variability are Monte-Carlo-like techniques. In Monte Carlo analysis, all process parameters can be varied individually or simultaneously in a more realistic approach. The Monte Carlo algorithm takes a random value within the range of each process parameter and performs circuit simulations repeatedly. The statistical characteristics are estimated from the responses. This technique is accurate but requires high computational resources and time. Thus, efforts are being put by different research groups to find alternative tools. If the variations are small, Green’s Function (GF) approach can be seen as a breakthrough methodology. One of the most open research fields regards "Variability of FinFET AC performances". One reason for the limited AC variability investigations is the lack of commercially available efficient simulation tools, especially those based on accurate physics-based analysis: in fact, the only way to perform AC variability analysis through commercial TCAD tools like Synopsys Sentaurus is through the so-called Monte Carlo approach, that when variations are deterministic, is more properly referred to as incremental analysis, i.e., repeated solutions of the device model with varying physical parameters. For each selected parameter, the model must be solved first in DC operating condition (working point, WP) and then linearized around the WP, hence increasing severely the simulation time. In this work, instead, we used GF approach, using our in-house Simulator "POLITO", to perform AC variability analysis, provided that variations are small, alleviating the requirement of double linearization and reducing the simulation time significantly with a slight trade-off in accuracy. Using this tool we have, for the first time addressed the dependency of FinFET AC parameters on the most relevant process variations, opening the way to its application to RF circuits. This work is ultimately dedicated to the successful implementation of RF stages in commercial applications by incorporating variability effects and controlling the degradation of AC parameters due to variability. We exploited the POLITO (in-house simulator) limited to 2D structures, but this work can be extended to the variability analysis of 3D FinFET structure. Also variability analysis of III-V Group structures can be addressed. There is also potentiality to carry out the sensitivity analysis for the other source of variations, e.g., thermal variations

Charge-Based Compact Modeling of Capacitances and Low-Frequency Noise in Organic Thin-Film Transistors

Els transistors orgànics de capa prima són candidats prometedors per a noves aplicacions electròniques a causa de la possibilitat de fabricar dispositius electrònics orgànics a baixes temperatures sobre substrats flexibles com el plàstic o el paper. Aquesta tesi doctoral tracta del desenvolupament d'un model compacte basat en la càrrega per a la descripció del comportament capacitiu i del soroll de baixa freqüència en transistors orgànics de capa prima. A partir d'un model de corrent continu existent, es deriven expressions per a les càrregues totals en condicions d'operació quasi estàtica. Els efectes no quasistàtics es capturen mitjançant diferents mètodes, com ara l'enfocament de segmentació de canals o funcions d'escalat depenents de la freqüència de les àrees del transistor on es calculen les càrregues. El model de les càrregues totals es verifica mitjançant mesures de capacitat d'un TFT orgànic esglaonat i per simulacions numèriques de TFT orgànics en les arquitectures esglaonades i coplanars mitjançant el simulador de dispositiu Sentaurus TCAD. Els models no quasistàtics es verifiquen mitjançant mesures d'admitància depenents de la freqüència d'un transistor esglaonat i per mesures de paràmetres de dispersió de transistors coplanars i esglalonats. El model compacte s'implementa en el llenguatge de descripció de hardware Verilog-A i la simulació d'un amplificador diferencial es compara amb les mesures, amb les quals es mostra un bon acord. El model de soroll es verifica mitjançant mesures de TFT orgànics esglalonats i simulacions TCAD. El model compacte mostra en general una bona concordança i flexibilitat en general pel que fa a l'arquitectura del dispositiu (per exemple, esglaonat o coplanar) i els materials utilitzats.Los transistores orgánicos de capa fina son candidatos prometedores para nuevas aplicaciones electrónicas debido a la posibilidad de fabricar dispositivos electrónicos orgánicos a bajas temperaturas en sustratos flexibles como plástico o papel. Esta tesis doctoral trata del desarrollo de un modelo compacto basado en la carga para la descripción del comportamiento capacitivo y el ruido de baja frecuencia en transistores orgánicos de capa fina. A partir de un modelo DC existente, se desarrollan expresiones para las cargas totales en condiciones de operación cuasiestáticas. Los efectos no cuasiestáticos se capturan mediante diferentes métodos, como la aproximación de segmentación del canal o las funciones de escalado dependientes de la frecuencia de las áreas del transistor donde se calculan las cargas. El modelo para las cargas totales se verifica mediante medidas de capacitancia de un TFT orgánico escalonado y mediante simulaciones numéricas de TFT orgánicos en las arquitecturas escalonada y coplanar utilizando el simulador de dispositivo TCAD Sentaurus. Los modelos no cuasiestáticos se verifican mediante medidas de admitancia dependientes de la frecuencia de un transistor escalonado y mediante medidas de parámetros de dispersión de transistores coplanares y escalonados. El modelo compacto se implementó en el lenguaje de descripción de hardware Verilog-A y la simulación de un amplificador diferencial se compara con medidas, observándose una buena concordancia. El modelo de ruido se verifica mediante medidas de TFT orgánicos escalonados y mediante simulaciones TCAD. El modelo compacto muestra en general una buena concordancia y flexibilidad con respecto a la arquitectura del dispositivo (p. ej. escalonado o coplanar) y los materiales utilizados.Organic thin-film transistors are promising candidates for novel electronics applications due to the possibility of fabricating organic electronic devices at low temperatures on flexible substrates like plastic or paper. This doctoral thesis deals with the development of a charge-based compact model for the description of the capacitive behavior and the low-frequency noise in organic thin-film transistors. Based on an existing DC model, expressions for the total charges under quasistatic operation conditions are derived. Non-quasistatic effects are captured by different methods, such as the channel-segmentation approach or frequency-dependent scaling functions of the areas in the transistor where charges are calculated. The model for the total charges is verified by capacitance measurements of a staggered organic TFT and by numerical simulations of organic TFTs in the staggered and coplanar architectures using the device simulator Sentaurus TCAD. The non-quasistatic models are verified by frequency-dependent admittance measurements of a staggered transistor and by scattering-parameter measurements of coplanar and staggered transistors. The compact model is implemented in the hardware description language Verilog-A and the simulation of a differential amplifier is compared to measurements, which shows a good agreement. The noise model is verified by measurements of staggered organic TFTs and by TCAD simulations. The compact model shows an overall good agreement and flexibility with respect to the device architecture (e. g. staggered or coplanar) and the used materials

Small signal Nonquasi-Static Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry

We present a physics-based closed form small signal Nonquasi-static (NQS) model for a long channel Common Double Gate MOSFET (CDG) by taking into account the asymmetry that may prevail between the gate oxide thickness. We use the unique quasi-linear relationship between the surface potentials along the channel to solve the governing continuity equation (CE) in order to develop the analytical expressions for the Y parameters. The Bessel function based solution of the CE is simplified in form of polynomials so that it could be easily implemented in any circuit simulator. The model shows good agreement with the TCAD simulation at-least till 4 times of the cut-off frequency for different device geometries and bias conditions