Buffer Sizing for 802.11 Based Networks

We consider the sizing of network buffers in 802.11 based networks. Wireless networks face a number of fundamental issues that do not arise in wired networks. We demonstrate that the use of fixed size buffers in 802.11 networks inevitably leads to either undesirable channel under-utilization or unnecessary high delays. We present two novel dynamic buffer sizing algorithms that achieve high throughput while maintaining low delay across a wide range of network conditions. Experimental measurements demonstrate the utility of the proposed algorithms in a production WLAN and a lab testbed.Comment: 14 pages, to appear on IEEE/ACM Transactions on Networkin

Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip

A Network on Chip (NoC) with end-to-end flow control is modelled by a cyclo-static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces. We show, for a range of NoC designs, that buffer sizes are determined with a run time comparable to existing analytical methods, and results comparable to exhaustive simulation

VERILOG Implementation of Reconfigurable Routers for Low Power

Network-on-chip (NoC) designs are based on a compromise among latency, power dissipation, or energy, and the balance is usually defined at design time. However, setting all parameters, such as buffer size, at design time can cause either excessive power dissipation (originated by router under utilization), or a higher latency. The situation worsens whenever the application changes its communication pattern, e.g., a portable phone downloads a new service. Large buffer sizes can ensure performance during the execution of different applications, but unfortunately, these same buffers are mainly responsible for the router total power dissipation. Another aspect is that by sizing buffers for the worst case latency incurs extra dissipation for the mean case, which is much more frequent. In this paper we propose the use of a reconfigurable router, where the buffer slots are dynamically allocated to increase router efficiency in an NoC, even under rather different communication loads. In the proposed architecture, the depth of each buffer word used in the input channels of the routers can be reconfigured at run time. The reconfigurable router allows up to 52% power savings, while maintaining the same performance as that of a homogeneous router, but using a 64% smaller buffer size

Selecting the Buffer Size for an IP Network Link

In this paper, we revisit the problem of selecting the buffer size for an IP network link. After a comprehensive overview of issues relevant to the link buffer sizing, we examine usefulness of existing guidelines for choosing the buffer size. Our analysis shows that the existing recommendations not only are difficult to implement in the context of IP networks but also can severely hurt interactive distributed applications. Then, we argue that the networking research community should change its way of thinking about the link buffer sizing problem: the focus should shift from optimizing performance for applications of a particular type to maximizing diversity of application types that IP networks can support effectively. To achieve this new objective, we propose using small buffers for IP network links

Leakage-Aware Interconnect for On-Chip Network

On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip. Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget. In this paper, we propose four leakage-aware interconnect schemes. Our schemes achieve 10.13%~63.57% active leakage savings and 12.35%~95.96% standby leakage savings across schemes while the delay penalty ranges from 0% to 4.69%.Comment: Submitted on behalf of EDAA (http://www.edaa.com/

How happy are your flows: an empirical study of packet losses in router buffers

Studies of Internet traffic have revealed that traffic is consistent with self-similar scaling, shows long-range dependence, and that flow sizes are consistent with heavytailed distributions. However, how such characteristics affect fundamental network properties such as buffer overflows and therefore the loss process and link utilization has not been explored in detail. Relying on advanced instrumentation via NetFPGA cards, we perform a sensitivity study of the packet loss process within routers for different network load levels, flow size distributions, and buffer sizes. We find that packet losses do not affect all flows similarly. Depending on the network load and the buffer sizes, some flows either suffer from significantly more drops or significantly less drops than the average loss rate. Very few flows actually observe a loss rate similar to the average loss rate. Therefore, any single flow is very unlikely to observe the global packet loss process. Furthermore, the loss process can exhibit scaling properties