Peningkatan Kinerja Jaringan Dengan Menggunakan Multi-Rule Algorithm

Algoritma pergantian adalah suatu mekanisme pergantian objek dalam cache yang lama dengan objek baru, dengan mekanisme  melakukan penghapusan objek sehingga mengurangi penggunaan bandwidth dan server load. Penghapusan dilakukan apabila cache penuh sehingga penyimpanan entri baru diperlukan. Secara umum algoritma FIFO, LRU dan LFU sering digunakan dalam pergantian objek, akan tetapi diperoleh suatu objek yang sering digunakan namun terhapus dalam pergantian cache sedangkan objek tersebut masih digunakan, akibatnya pada waktu klien melakukan permintaan dibutuhkan waktu yang lama dalam browsing objek. Untuk mengatasi masalah tersebut dilakukan kombinasi algoritma pergantian cache Multi-Rule Algorithm, dalam bentuk algoritma kombinasi ganda FIFO-LRU dan triple FIFO-LRU-LFU. Algoritma Mural (Multi-Rule Algorithm) menghasilkan respon pada cache size 200 MB dengan waktu tanggapan rata-rata berturut-turut 56,33 dan 42 ms, sedangkan pada algoritma tunggal memerlukan waktu tanggapan rata-rata 77 ms. Sehingga Multi-Rule Algorithm dapat meningkatkan kinerja terhadap waktu penundaan, throughput, dan hit rate. Dengan demikian, algoritma pergantian cache Mural, sangat direkomendasikan untuk meningkatkan akses klien. AbstractSubstitution algorithm is a mechanism to replace objects in the old cache with new objects, with a mechanism to delete objects so that it reduces bandwidth usage and server load. Deletion is done when the cache is full so saving new entries is needed. In general, FIFO, LRU and LFU algorithms are often used in object changes, but an object that is often used but is deleted in the cache changes while the object is still being used, consequently when the client makes a request it takes a long time to browse the object. To overcome this problem a combination of Multi-Rule Algorithm cache replacement algorithms is performed, in the form of a double combination algorithm FIFO-LRU and triple FIFO-LRU-LFU. The Mural algorithm (Multi-Rule Algorithm) produces a response on a cache size of 200 MB with an average response time of 56.33 and 42 ms respectively, whereas a single algorithm requires an average response time of 77 ms. So the Multi-Rule Algorithm can improve the performance of the delay, throughput, and hit rate. Thus, the Mural cache change algorithm, is highly recommended to improve client access

Concertina: Squeezing in cache content to operate at near-threshold voltage

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Scaling supply voltage to values near the threshold voltage allows a dramatic decrease in the power consumption of processors; however, the lower the voltage, the higher the sensitivity to process variation, and, hence, the lower the reliability. Large SRAM structures, like the last-level cache (LLC), are extremely vulnerable to process variation because they are aggressively sized to satisfy high density requirements. In this paper, we propose Concertina, an LLC designed to enable reliable operation at low voltages with conventional SRAM cells. Based on the observation that for many applications the LLC contains large amounts of null data, Concertina compresses cache blocks in order that they can be allocated to cache entries with faulty cells, enabling use of 100 percent of the LLC capacity. To distribute blocks among cache entries, Concertina implements a compression- and fault-aware insertion/replacement policy that reduces the LLC miss rate. Concertina reaches the performance of an ideal system implementing an LLC that does not suffer from parameter variation with a modest storage overhead. Specifically, performance degrades by less than 2 percent, even when using small SRAM cells, which implies over 90 percent of cache entries having defective cells, and this represents a notable improvement on previously proposed techniques.Peer ReviewedPostprint (author's final draft