Algebraic Construction and Cryptographic Properties of Rijndael Substitution Box

Rijndael algorithm was selected as the advanced encryption standard in 2001 after five year long security evaluation; it is well proven in terms of its strength and efficiency. The substitution box is the back bone of the cipher and its strength lies in the simplicity of its algebraic construction. The present paper is a study of the construction of Rijndael Substitution box and the effect of varying the design components on its cryptographic properties.Defence Science Journal, 2012, 62(1), pp.32-37, DOI:http://dx.doi.org/10.14429/dsj.62.143

FPGA Simulation of Type-3 Feistel Network of The 128 bits Block Size Improved Blowfish Cryptographic Encryption

Reprogrammable devices such as Field Programmable Gate Arrays (FPGAs)are highly attractive options for hardware implementations of encryption algorithmsas they provide cryptographic algorithm agility, physical security, and potentiallymuch higher performance than software solutions , therefore this paper investigates ahardware design to efficiently implement block ciphers in VHDL based on FPGA’s.This hardware design is applied to the new secret-key block cipher called 128-bitsimproved Blowfish is proposed which is an evolutionary improvement of 64-bitsBlowfish designed to meet the requirements of the Advanced Encryption Standard(AES) to increase security and to improve performance. The proposed algorithm willbe used a variable key size up to 192 bytes. It is a Type-3 Feistel network iteratedsimple function 16 times.The resources used to implement the design just described are: the VHDLhardware description language, an FPGA platform from Xilinx and the XilinxSynthesis Technology (XST) software synthesis tools that belong to ISE 9.2i package.The device of choice is the XCV600-4fg680 belonging to the Virtex family ofdevices.In this paper, a pipeline and sequential methods are used to get a highthrougput (2.893Gbps) and a low area hardware design respectively

A fully pipelined memoryless 17.8 Gbps AES-128 encryptor

A fully pipelined implementation of the Advanced Encryption Stan-dard encryption algorithm with 128-bit input and key length (AES-128) was implemented on Xilinx ’ Virtex-E and Virtex-II devices. The design is called SIG-AES-E and it implements the S-boxes combinatorially and thus requires no internal memory. It is con-cluded, that SIG-AES-E is faster than other published FPGA-based implementations of the AES-128 encryption algorithm. Categories and Subject Descriptor