Programmable neural logic

Circuits of threshold elements (Boolean input, Boolean output neurons) have been shown to be surprisingly powerful. Useful functions such as XOR, ADD and MULTIPLY can be implemented by such circuits more efficiently than by traditional AND/OR circuits. In view of that, we have designed and built a programmable threshold element. The weights are stored on polysilicon floating gates, providing long-term retention without refresh. The weight value is increased using tunneling and decreased via hot electron injection. A weight is stored on a single transistor allowing the development of dense arrays of threshold elements. A 16-input programmable neuron was fabricated in the standard 2 μm double-poly, analog process available from MOSIS. We also designed and fabricated the multiple threshold element introduced in [5]. It presents the advantage of reducing the area of the layout from O(n^2) to O(n); (n being the number of variables) for a broad class of Boolean functions, in particular symmetric Boolean functions such as PARITY. A long term goal of this research is to incorporate programmable single/multiple threshold elements, as building blocks in field programmable gate arrays

Floating-Gate MOS Synapse Transistors

Our goal is to develop silicon learning systems. One impediment to achieving this goal has been the lack of a simple circuit element combining nonvolatile analog memory storage with locally computed memory updates. Existing circuits [63, 132] typically are large and complex; the nonvolatile floating-gate devices, such as EEPROM transistors. typically are optimized for binary-valued storage [17], and do not compute their own memory updates. Although floating-gate transistors can provide nonvolatile analog storage [1, 15], because writing the memory entails the difficult process of moving electrons through Si0_2, these devices have not seen wide use as memory elements in silicon learning systems

Multiple Threshold Neural Logic

We introduce a new Boolean computing element related to the Linear Threshold element, which is the Boolean version of the neuron. Instead of the sign function, it computes an arbitrary (with polynomialy many transitions) Boolean function of the weighted sum of its inputs. We call the new computing element an LT M element, which stands for Linear Threshold with Multiple transitions. The paper consists of the following main contributions related to our study of LTM circuits: (i) the creation of efficient designs of LTM circuits for the addition of a multiple number of integers and the product of two integers. In particular, we show how to compute the addition of m integers with a single layer of LT M elements. (ii) a proof that the area of the VLSI layout is reduced from O(n^2) in LT circuits to O(n) in LTM circuits, for n inputs symmetric Boolean functions, and (iii) the characterization of the computing power of LT M relative to LT circuits

Analog VLSI-Based Modeling of the Primate Oculomotor System

One way to understand a neurobiological system is by building a simulacrum that replicates its behavior in real time using similar constraints. Analog very large-scale integrated (VLSI) electronic circuit technology provides such an enabling technology. We here describe a neuromorphic system that is part of a long-term effort to understand the primate oculomotor system. It requires both fast sensory processing and fast motor control to interact with the world. A one-dimensional hardware model of the primate eye has been built that simulates the physical dynamics of the biological system. It is driven by two different analog VLSI chips, one mimicking cortical visual processing for target selection and tracking and another modeling brain stem circuits that drive the eye muscles. Our oculomotor plant demonstrates both smooth pursuit movements, driven by a retinal velocity error signal, and saccadic eye movements, controlled by retinal position error, and can reproduce several behavioral, stimulation, lesion, and adaptation experiments performed on primates

Analogue micropower FET techniques review

A detailed introduction to published analogue circuit design techniques using Si and Si/SiGe FET devices for very low-power applications is presented in this review. The topics discussed include sub-threshold operation in FET devices, micro-current mirrors and cascode techniques, voltage level-shifting and class-AB operation, the bulk-drive approach, the floating-gate method, micropower transconductance-capacitance and log-domain filters and strained-channel FET technologies

Analysis and Characterization of Single-Poly Floating Gate Devices in 0.35um PDSOI Process

The purpose of this thesis is to demonstrate a single-poly Floating Gate Device (FGD) in 0.35 m Partially Depleted Silicon On Insulator (PDSOI) process for use in analog circuits for post process trimming. Floating gate devices with different aspect ratios have been fabricated to facilitate this behavioral study in PDSOI process. Fundamentals of floating gate devices, the advantages and disadvantages of PDSOI compared to bulk CMOS with respect to single-poly floating gate devices are discussed. Various experiments on behavior and performance of threshold voltage have been conducted and its variation with programming/erasing time and amplitude has been analyzed. The single-poly FGD’s on-resistance variation and hysteresis behavior with threshold voltage has been documented. A mathematical relation between FGD’s on-resistance and threshold voltage has been experimentally derived. Intrinsic data retention has been estimated through extrapolation of experimental data. A process independent MATLAB simulation model has been successfully developed for understanding the threshold voltage time dependence characteristics. And finally, this work has shown that programmable or post-process trimmable analog circuits can be implemented in SOI using single-poly FGDs as programmable resistive elements. A SOI programmable beta-multiplier current reference has been successfully demonstrated using the singlepoly FGD as a resistive element

A floating-gate MOS learning array with locally computed weight updates

We have demonstrated on-chip learning in an array of floating-gate MOS synapse transistors. The array comprises one synapse transistor at each node, and normalization circuitry at the row boundaries. The array computes the inner product of a column input vector and a stored weight matrix. The weights are stored as floating-gate charge; they are nonvolatile, but can increase when we apply a row-learn signal. The input and learn signals are digital pulses; column input pulses that are coincident with row-learn pulses cause weight increases at selected synapses. The normalization circuitry forces row synapses to compete for floating-gate charge, bounding the weight values. The array simultaneously exhibits fast computation and slow adaptation: The inner product computes in 10 μs, whereas the weight normalization takes minutes to hours

CMOS programmable analog memory-cell array using floating-gate circuits

Journal ArticleThe complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off-chip. Moving parameter storage on-chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip nonvolatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and hot-electron injection to program values. We have fabricated two versions of this design: one with an nFET injection mechanism and one with a pFET injection mechanism. With these designs, we achieve greater than 13-bit output precision with a 39-dB power-supply rejection ratio and no crosstalk between memory cells

Neuromorphic visual artificial synapse in-memory computing systems based on GeOx-coated MXene nanosheets

Artificial synapses with light signal perception capability offer the ability to neuromorphic visual signal processing system on demand. In light of the excellent optical and electrical characteristics, the low-dimensional materials have become one of the most favorable candidates of the key component for optoelectronic artificial synapses. Previously, our group originally proposed the synthesis of germanium oxide-coated MXene nanosheets. In this work, we further applied this technology into the optoelectronic synaptic thin-film transistors for the first time. The devices exhibited the adjustable postsynaptic current behaviors under the visible light inputs. Moreover, the potentiation and depression operation modes of the devices further improved the application potential of the devices in mimicking biological synapses. Regulated by the wavelength of incident lights, the proposed artificial synapse could effectively help detect the target area of the image. Eventually, we further showed the results of the devices in the projects of neural network computing task. The long-term potentiation/depression characteristics of the conductance were applied to the synaptic weight matrix for image identification and path recognition tasks. By adding knowledge transfer in the process of recognition, the epoch required for convergence has been greatly reduced. The result of high noise tolerance revealed the great potential of the proposed transistors in establishing high-efficiency and robustness hardware neuromorphic systems for in-memory computing