Switched-compensation technique in switched-capacitor circuits for achieving fast settling performance

Resolving stability issue is one of the major challenges in designing a perfect op-amp, the most widely used analog circuit block. Many compensation techniques have been proposed to improve the stability performance of op amps, but virtually all these techniques were developed for continuous-time applications and subsequently applied to discrete-time applications (e.g., switched-capacitor circuits). Since the early 1980s, an increasing number of op-amps have been used in switched-capacitor circuits with no special compensation method applied. Consequently, there remains a need to explore the possibility of designing a unique compensation method specifically for switched-capacitor use. A new switched-compensation technique (SCT) is proposed for switched-capacitor circuit applications in which high speed is a critical index of performance. In general, designers must deal with trade-offs among accuracy, speed, and power dissipation. SCT avoids traditional approaches of designing high-speed, high-gain operational amplifiers that are in many cases technology-limited. Instead, it modifies the switched-capacitor circuit structure to use the under-damped response of the system, usually regarded as a drawback. SCT is introduced as a novel solution for achieving fast settling performance and lower quiescent power dissipation while guaranteeing almost equivalent accuracy. SCT can be easily implemented in flip-around switched-capacitor amplifier circuits. This paper explains SCT principle and implementation applied to multiplying-digital-to-analog converters (MDACs) as a proof of concept. Simulation results based on an IBM 0.13um CMOS process are presented. Compared with a conventional switched-capacitor amplifier, a SCT-based implementation reduces the quiescent power consumption by half and settling time within 1% error by 60%

Design of a High Performance Silicon Carbide CMOS Operational Amplifier

This thesis presents the design, simulation, layout and test results of a silicon carbide (SiC) CMOS two-stage operational amplifier (op amp) with NMOS input stage. The circuit has been designed to provide a stable open-loop voltage gain (60 dB), unity-gain bandwidth (around 5 MHz) and maintain a high CMRR and PSRR within a useful input common mode range over process corners and a wide temperature range (25 °C - 300 °C). Between the two stages a Miller compensation topology is placed to improve the phase margin (around 45°). Due to the comparatively high threshold voltage values of transistors in SiC, the power supply is maintained at 15 V. There is a maximum of 21% variation in DC gain from 25 °C to 275 °C and the unity-gain bandwidth and slew rate improves with higher temperature. The major application area of this op amp is in high temperature environments where silicon (Si) integrated circuits (IC) fail to perform. In addition, the design of a second version of the operational amplifier is covered, which aims to provide more functionality and improved performance

Design of Two-Stage Operational Amplifier using Indirect Feedback Frequency Compensation

This thesis work details the designing process of two silicon two-stage operational amplifiers with indirect feedback compensation and with Miller compensation technique. The main objective of this thesis is to study the advantages of indirect feedback compensation in comparison with Miller compensation and how this technique can be applied to meet certain design specifications. The operational amplifiers are designed with 130 nm Silicon Germanium CMOS process ideally for temperature range of 25°C to 300°C. The two op-amps are designed to have a DC gain of about 70 dB and 60 degrees of phase margin. The indirect feedback compensation design showed similar simulation results as the Miller compensation technique; nevertheless, it showed a reduce in the compensation capacitor size, meaning a smaller design area, and an improvement in the phase margin from the LHP zero. Also, the proposed design showed a higher unity gain frequency. Further analysis of indirect feedback frequency compensation on multistage amplifiers (greater than two) should be conducted to analyze the potential of this compensation method under more complex compensation against the commonly used Miller technique

Frequency compensation of CMOS operational amplifier.

Ho Kin-Pui.Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.Includes bibliographical references (leaves 92-95).Abstracts in English and Chinese.Abstract --- p.2摘要 --- p.4Acknowledgements --- p.5Table of Contents --- p.6List of Figures --- p.10List of Tables --- p.14Chapter Chapter 1 --- Introduction --- p.15Overview --- p.15Objective --- p.17Thesis Organization --- p.17Chapter Chapter 2 --- Fundamentals of Operational Amplifier --- p.19Chapter 2.1 --- Definitions of Commonly Used Figures --- p.19Chapter 2.1.1 --- Input Differential Voltage Range --- p.19Chapter 2.1.2 --- Maximum Output Voltage Swing --- p.20Chapter 2.1.3 --- Input Common Mode Voltage Range --- p.20Chapter 2.1.4 --- Input Offset Voltage --- p.20Chapter 2.1.5 --- Gain Bandwidth Product --- p.21Chapter 2.1.6 --- Phase Margin --- p.22Chapter 2.1.7 --- Slew Rate --- p.22Chapter 2.1.8 --- Settling Time --- p.23Chapter 2.1.9 --- Common Mode Rejection Ratio --- p.23Chapter 2.2 --- Frequency Compensation of Operational Amplifier --- p.24Chapter 2.2.1 --- Overview --- p.24Chapter 2.2.2 --- Miller Compensation --- p.25Chapter Chapter 3 --- CMOS Current Feedback Operational Amplifier --- p.27Chapter 3.1 --- Introduction --- p.27Chapter 3.2 --- Current Feedback Operational Amplifier with Active Current Mode Compensation --- p.28Chapter 3.2.1 --- Circuit Description --- p.29Chapter 3.2.2 --- Small Signal analysis --- p.32Chapter 3.2.3 --- Simulation Results --- p.34Chapter Chapter 4 --- Reversed Nested Miller Compensation --- p.38Chapter 4.1 --- Introduction --- p.38Chapter 4.2 --- Frequency Response --- p.39Chapter 4.2.1 --- Gain-bandwidth product --- p.40Chapter 4.2.2 --- Right half complex plane zero --- p.40Chapter 4.2.3 --- The Pair of Complex Conjugate Poles --- p.42Chapter 4.3 --- Components Sizing --- p.47Chapter 4.4 --- Circuit Simulation --- p.48Chapter Chapter 5 --- Enhancement Technique for Reversed Nested Miller Compensation --- p.54Chapter 5.1 --- Introduction --- p.54Chapter 5.2 --- Working principle of the proposed circuit --- p.54Chapter 5.2.1 --- The introduction of nulling resistor --- p.55Chapter 5.2.2 --- The introduction of a voltage buffer --- p.55Chapter 5.2.3 --- Small Signal Analysis --- p.57Chapter 5.2.4 --- Sign Inversion of the RHP Zero with Nulling Resistor --- p.59Chapter 5.2.5 --- Frequency Multiplication of the Complex Conjugate Poles --- p.60Chapter 5.2.6 --- Stability Conditions --- p.63Chapter 5.3 --- Performance Comparison --- p.67Chapter 5.4 --- Conclusion: --- p.70Chapter 5.4.1 --- Circuit Modifications: --- p.70Chapter 5.4.2 --- Advantages: --- p.71Chapter Chapter 6 --- Physical Design of Operational Amplifier --- p.72Chapter 6.1 --- Introduction --- p.72Chapter 6.2 --- Transistor Layout Techniques --- p.72Chapter 6.2.1 --- Multi-finger Layout Technique --- p.72Chapter 6.2.2 --- Common-Centroid Structure --- p.73Chapter 6.3 --- Layout Techniques of Passive Components --- p.74Chapter 6.3.1 --- Capacitor Layout --- p.74Chapter 6.3.2 --- Resistor Layout --- p.75Chapter Chapter 7 --- Measurement Results --- p.77Chapter 7.1 --- Overview --- p.77Chapter 7.2 --- Measurement Results for the Current Feedback Operational Amplifier --- p.77Chapter 7.2.1 --- Frequency Response of the inverting amplifier --- p.77Chapter 7.3 --- Measurement Results for the Three-Stage Operational Amplifier --- p.80Chapter 7.3.1 --- Input Offset Voltage Measurement --- p.80Chapter 7.3.2 --- Input Common Mode Range Measurement --- p.80Chapter 7.3.3 --- Gain Band width Measurement --- p.81Chapter 7.3.4 --- DC Gain measurement --- p.85Chapter 7.3.5 --- Slew Rate Measurement --- p.87Chapter 7.3.6 --- Phase Margin --- p.88Chapter 7.3.7 --- Performance Summary --- p.89Chapter Chapter 8 --- Conclusions --- p.90Chapter Chapter 9 --- Appendix --- p.9

Analog multiply and accumulate FPA readout circuit with digital multiply and sign maintenance

The high bandwidth and power needed to process the data coming from modern high resolution focal plane arrays leads to the necessity for fast and efficient read out and data processing. A system that performs block recognition and image classification with efficiency and low latency is presented. The system is comprised of an analog signal processor that will be integrated into the read out integrated circuit. This enables the capability to read out the focal plane array information and process it completely in the analog domain in a comparably very small amount of operational steps. The steps and techniques of the design flow, including definition of problem, concepts and design of system architecture, simulation of system, and analog lay out practices are covered

An improved reversed miller compensation technique for three-stage CMOS OTAs with double pole-zero cancellation and almost single-pole frequency response

This paper presents an improved reversed nested Miller compensation technique exploiting a single additional feed-forward stage to obtain double pole-zero cancellation and ideally single-pole behavior, in a three-stage Miller amplifier. The approach allows designing a three-stage operational transconductance amplifier (OTA) with one dominant pole and two (ideally) mutually cancelling pole-zero doublets. We demonstrate the robustness of the proposed cancellation technique, showing that it is not significantly influenced by process and temperature variations. The proposed design equations allow setting the unity-gain frequency of the amplifier and the complex poles' resonance frequency and quality factor. We introduce the notion of bandwidth efficiency to quantify the OTA performance with respect to a telescopic cascode OTA for given load capacitance and power consumption constraints and demonstrate analytically that the proposed approach allows a bandwidth efficiency that can ideally approach 100%. A CMOS implementation of the proposed compensation technique is provided, in which a current reuse scheme is used to reduce the total current consumption. The OTA has been designed using a 130-nm CMOS process by STMicroelectronics and achieves a DC gain larger than 120 dB, with almost single-pole frequency response. Monte Carlo simulations have been performed to show the robustness of the proposed approach to process, voltage, and temperature (PVT) variations and mismatches

Indirect Compensation Techniques for Three-Stage CMOS Op-Amps

As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by vertically stacking (i.e. cascoding) transistors becomes less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low supply voltage processes. This paper discusses new design techniques for the realization of three-stage op-amps. The proposed and experimentally verified op-amps, fabricated in 500 nm CMOS, typically exhibit 30 MHz unity-gain frequency, near 100ns transient settling and 72° phase-margin for 500pF load. This results in significantly higher op-amp performance metrics over the traditional op-amp designs while at the same time having smaller layout area

Indirect Compensation Techniques for Three-Stage Fully-Differential Op-Amps

As CMOS technology continues to evolve, thesupply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by cascoding become less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low supply voltage processes. This paper discusses indirect compensation techniques for op-amps using split-length devices. A reversed-nested indirect compensated (RNIC) topology, employing double pole-zero cancellation, is illustrated for the design of three-stage op-amps. The RNIC topology is then extended to the design of three-stage fully-differential op-amps. Novel three-stage fully-differential gain-stage cascade structures are presented with efficient common mode feedback (CMFB) stabilization. Simulation results are presented for the designed RNIC fullydifferential three-stage op-amps. The fully-differential three-stage op-amps, designed in 0.5 μm CMOS, typically exhibit 18 MHz unity-gain frequency, 82 dB open-loop DC gain, nearly 300 ns transient settling and 72° phase-margin for a 500 pF load

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio