An Efficient Test Relaxation Technique for Synchronous Sequential Circuits

Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. Test-set relaxation can improve the efficiency of both test compression and test compaction. In addition, the relaxation process can identify selfinitializing test sequences for synchronous sequential circuits. In this paper, we propose an efficient test relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set

Test Cost Reduction for Logic Circuits——Reduction of Test Data Volume and Test Application Time——

論理回路の大規模化とともに,テストコストの増大が深刻な問題となっている.特に大規模な論理回路では,テストデータ量やテスト実行時間の削減が,テストコスト削減の重要な課題である.本論文では,高い故障検出率のテストパターンをできるだけ少ないテストベクトル数で実現するためのテストコンパクション技術,付加ハードウェアによるテストデータの展開・伸長を前提に圧縮を行うテストコンプレッション技術,及び,スキャン設計回路におけるテスト実行時間削減技術について概説する

ICCAD '96 Simulation-Based Techniques for Dynamic Test Sequence Compaction

Abstract Simulation-based t e chniques for dynamic compaction of test sequences are proposed. The rst technique uses a fault simulator to remove test vectors from the partially-specied test sequence generated by a deterministic test generator if the vectors are not needed t o detect the target fault, considering that the circuit state may be known. The second technique uses genetic algorithms to ll the unspecied bits in the partially-specied test sequence i n order to increase the number of faults detected b y the sequence. Signicant reductions in test set sizes were observed for all benchmark circuits studied. Fault coverages improved for many of the circuits, and execution times often dropped as well, since fewer faults had to be targeted by the computation-intensive deterministic test generator