Systematic Physics-Compliant Analysis of Over-the-Air Channel Equalization in RIS-Parametrized Wireless Networks-on-Chip

Wireless networks-on-chip (WNoCs) are an enticing complementary interconnect technology for multi-core chips but face severe resource constraints. Being limited to simple on-off-keying modulation, the reverberant nature of the chip enclosure imposes limits on allowed modulation speeds in sight of inter-symbol interference, casting doubts on the competitiveness of WNoCs as interconnect technology. Fortunately, this vexing problem was recently overcome by parametrizing the on-chip radio environment with a reconfigurable intelligent surface (RIS). By suitably configuring the RIS, selected channel impulse responses (CIRs) can be tuned to be (almost) pulse-like despite rich scattering thanks to judiciously tailored multi-bounce path interferences. However, the exploration of this "over-the-air" (OTA) equalization is thwarted by (i) the overwhelming complexity of the propagation environment, and (ii) the non-linear dependence of the CIR on the RIS configuration, requiring a costly and lengthy full-wave simulation for every optimization step. Here, we show that a reduced-basis physics-compliant model for RIS-parametrized WNoCs can be calibrated with a single full-wave simulation. Thereby, we unlock the possibility of predicting the CIR for any RIS configuration almost instantaneously without any additional full-wave simulation. We leverage this new tool to systematically explore OTA equalization in RIS-parametrized WNoCs regarding the optimal choice of delay time for the RIS-shaped CIR's peak. We also study the simultaneous optimization of multiple on-chip wireless links for broadcasting. Looking forward, the introduced tools will enable the efficient exploration of various types of OTA analog computing in RIS-parametrized WNoCs.Comment: 10 pages, 7 figures, submitted to an IEEE Journa

2009 Index IEEE Antennas and Wireless Propagation Letters Vol. 8

This index covers all technical items - papers, correspondence, reviews, etc. - that appeared in this periodical during the year, and items from previous years that were commented upon or corrected in this year. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author\u27s name. The primary entry includes the coauthors\u27 names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author\u27s name, the publication abbreviation, month, and year, and inclusive pages. Note that the item title is found only under the primary entry in the Author Index

2008 Index IEEE Transactions on Control Systems Technology Vol. 16

This index covers all technical items - papers, correspondence, reviews, etc. - that appeared in this periodical during the year, and items from previous years that were commented upon or corrected in this year. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author\u27s name. The primary entry includes the coauthors\u27 names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author\u27s name, the publication abbreviation, month, and year, and inclusive pages. Note that the item title is found only under the primary entry in the Author Index

Architecting a One-to-many Traffic-Aware and Secure Millimeter-Wave Wireless Network-in-Package Interconnect for Multichip Systems

With the aggressive scaling of device geometries, the yield of complex Multi Core Single Chip(MCSC) systems with many cores will decrease due to the higher probability of manufacturing defects especially, in dies with a large area. Disintegration of large System-on-Chips(SoCs) into smaller chips called chiplets has shown to improve the yield and cost of complex systems. Therefore, platform-based computing modules such as embedded systems and micro-servers have already adopted Multi Core Multi Chip (MCMC) architectures overMCSC architectures. Due to the scaling of memory intensive parallel applications in such systems, data is more likely to be shared among various cores residing in different chips resulting in a significant increase in chip-to-chip traffic, especially one-to-many traffic. This one-to-many traffic is originated mainly to maintain cache-coherence between many cores residing in multiple chips. Besides, one-to-many traffics are also exploited by many parallel programming models, system-level synchronization mechanisms, and control signals. How-ever, state-of-the-art Network-on-Chip (NoC)-based wired interconnection architectures do not provide enough support as they handle such one-to-many traffic as multiple unicast trafficusing a multi-hop MCMC communication fabric. As a result, even a small portion of such one-to-many traffic can significantly reduce system performance as traditional NoC-basedinterconnect cannot mask the high latency and energy consumption caused by chip-to-chipwired I/Os. Moreover, with the increase in memory intensive applications and scaling of MCMC systems, traditional NoC-based wired interconnects fail to provide a scalable inter-connection solution required to support the increased cache-coherence and synchronization generated one-to-many traffic in future MCMC-based High-Performance Computing (HPC) nodes. Therefore, these computation and memory intensive MCMC systems need an energy-efficient, low latency, and scalable one-to-many (broadcast/multicast) traffic-aware interconnection infrastructure to ensure high-performance. Research in recent years has shown that Wireless Network-in-Package (WiNiP) architectures with CMOS compatible Millimeter-Wave (mm-wave) transceivers can provide a scalable, low latency, and energy-efficient interconnect solution for on and off-chip communication. In this dissertation, a one-to-many traffic-aware WiNiP interconnection architecture with a starvation-free hybrid Medium Access Control (MAC), an asymmetric topology, and a novel flow control has been proposed. The different components of the proposed architecture are individually one-to-many traffic-aware and as a system, they collaborate with each other to provide required support for one-to-many traffic communication in a MCMC environment. It has been shown that such interconnection architecture can reduce energy consumption and average packet latency by 46.96% and 47.08% respectively for MCMC systems. Despite providing performance enhancements, wireless channel, being an unguided medium, is vulnerable to various security attacks such as jamming induced Denial-of-Service (DoS), eavesdropping, and spoofing. Further, to minimize the time-to-market and design costs, modern SoCs often use Third Party IPs (3PIPs) from untrusted organizations. An adversary either at the foundry or at the 3PIP design house can introduce a malicious circuitry, to jeopardize an SoC. Such malicious circuitry is known as a Hardware Trojan (HT). An HTplanted in the WiNiP from a vulnerable design or manufacturing process can compromise a Wireless Interface (WI) to enable illegitimate transmission through the infected WI resulting in a potential DoS attack for other WIs in the MCMC system. Moreover, HTs can be used for various other malicious purposes, including battery exhaustion, functionality subversion, and information leakage. This information when leaked to a malicious external attackercan reveals important information regarding the application suites running on the system, thereby compromising the user profile. To address persistent jamming-based DoS attack in WiNiP, in this dissertation, a secure WiNiP interconnection architecture for MCMC systems has been proposed that re-uses the one-to-many traffic-aware MAC and existing Design for Testability (DFT) hardware along with Machine Learning (ML) approach. Furthermore, a novel Simulated Annealing (SA)-based routing obfuscation mechanism was also proposed toprotect against an HT-assisted novel traffic analysis attack. Simulation results show that,the ML classifiers can achieve an accuracy of 99.87% for DoS attack detection while SA-basedrouting obfuscation could reduce application detection accuracy to only 15% for HT-assistedtraffic analysis attack and hence, secure the WiNiP fabric from age-old and emerging attacks

Fluidic, Solid-State, and Hybrid Reconfiguration Techniques in a Frequency and Polarization Reconfigurable Antenna

This work presents the development of a hybrid reconfiguration technique used to achieve both frequency and polarization diversity in a 2.4 – 2.5 GHz microstrip antenna. This hybrid solution for the first time combines current state-of-the-art fluidic and solid-state reconfiguration mechanisms in a collaborative effort. Two orthogonally-crossed and co-located narrow microstrip patches with gap discontinuities separating a central probe-fed section from the radiating slots provides the base antenna structure. The fluidic mechanisms use high strength dielectric fluids or liquid metal loaded across the gap discontinuities and the solid-state mechanisms uses readily available RF PIN and varactor diodes integrated across the gaps to enable reconfiguration. Accurate and robust circuit modeling concepts are presented to provide insight on antenna performance and loss mechanisms from each reconfiguration technique. A polarization-only reconfigurable version of this antenna utilizing dielectric fluids, RF PIN didoes, and liquid metal in separate design iterations were examined to introduce design and circuit modeling concepts and provide a first comparison between the reconfiguration techniques. While all iterations achieved good linear polarization switching, dielectric fluids and the RF PIN didoes are found to have large negative impacts on radiation performance due to ohmic losses (radiation efficiencies between 8 – 35%). In the liquid metal iteration, ohmic losses are significantly reduced to boost radiation efficiencies near that of a tradition patch antenna (near 80%). The hybrid reconfiguration solution utilizes liquid metal and solid-state varactors for polarization and frequency diversity, respectively. Non-hybrid design iterations using only dielectric fluids and solid-state RF PIN diodes with varactors provide a comparison between all reconfiguration techniques and demonstrate the advantages of the hybrid solution. It was found that broadly variable dielectric strength fluids used as a sole reconfiguration mechanism can achieve a wide frequency tuning range of 700 MHz, maintain linear polarization switching, and have radiation efficiencies near 60%. However, the fluids must have loss tangents less than 0.02 and are currently not readily available. The RF PIN and varactor diode combination provides a realizable solution, however, suffers from excessive DC control power requirements, a limited tuning range of 100 MHz, and low radiation efficiency around 16%. The hybrid solution combines the best aspects of all subsequent design iterations to achieve a realizable frequency and polarization reconfigurable antenna with a tuning range of 263 MHz and 41.7% radiation efficiency average across reconfiguration states

Temperature Evaluation of NoC Architectures and Dynamically Reconfigurable NoC

Advancements in the field of chip fabrication led to the integration of a large number of transistors in a small area, giving rise to the multi–core processor era. Massive multi–core processors facilitate innovation and research in the field of healthcare, defense, entertainment, meteorology and many others. Reduction in chip area and increase in the number of on–chip cores is accompanied by power and temperature issues. In high performance multi–core chips, power and heat are predominant constraints. High performance massive multicore systems suffer from thermal hotspots, exacerbating the problem of reliability in deep submicron technologies. High power consumption not only increases the chip temperature but also jeopardizes the integrity of the system. Hence, there is a need to explore holistic power and thermal optimization and management strategies for massive on–chip multi–core environments. In multi–core environments, the communication fabric plays a major role in deciding the efficiency of the system. In multi–core processor chips this communication infrastructure is predominantly a Network–on–Chip (NoC). Tradition NoC designs incorporate planar interconnects as a result these NoCs have long, multi–hop wireline links for data exchange. Due to the presence of multi–hop planar links such NoC architectures fall prey to high latency, significant power dissipation and temperature hotspots. Networks inspired from nature are envisioned as an enabling technology to achieve highly efficient and low power NoC designs. Adopting wireless technology in such architectures enhance their performance. Placement of wireless interconnects (WIs) alters the behavior of the network and hence a random deployment of WIs may not result in a thermally optimal solution. In such scenarios, the WIs being highly efficient would attract high traffic densities resulting in thermal hotspots. Hence, the location and utilization of the wireless links is a key factor in obtaining a thermal optimal highly efficient Network–on–chip. Optimization of the NoC framework alone is incapable of addressing the effects due to the runtime dynamics of the system. Minimal paths solely optimized for performance in the network may lead to excessive utilization of certain NoC components leading to thermal hotspots. Hence, architectural innovation in conjunction with suitable power and thermal management strategies is the key for designing high performance and energy–efficient multicore systems. This work contributes at exploring various wired and wireless NoC architectures that achieve best trade–offs between temperature, performance and energy–efficiency. It further proposes an adaptive routing scheme which factors in the thermal profile of the chip. The proposed routing mechanism dynamically reacts to the thermal profile of the chip and takes measures to avoid thermal hotspots, achieving a thermally efficient dynamically reconfigurable network on chip architecture

Computing and communications for the software-defined metamaterial paradigm: a context analysis

Metamaterials are artificial structures that have recently enabled the realization of novel electromagnetic components with engineered and even unnatural functionalities. Existing metamaterials are specifically designed for a single application working under preset conditions (e.g., electromagnetic cloaking for a fixed angle of incidence) and cannot be reused. Software-defined metamaterials (SDMs) are a much sought-after paradigm shift, exhibiting electromagnetic properties that can be reconfigured at runtime using a set of software primitives. To enable this new technology, SDMs require the integration of a network of controllers within the structure of the metamaterial, where each controller interacts locally and communicates globally to obtain the programmed behavior. The design approach for such controllers and the interconnection network, however, remains unclear due to the unique combination of constraints and requirements of the scenario. To bridge this gap, this paper aims to provide a context analysis from the computation and communication perspectives. Then, analogies are drawn between the SDM scenario and other applications both at the micro and nano scales, identifying possible candidates for the implementation of the controllers and the intra-SDM network. Finally, the main challenges of SDMs related to computing and communications are outlined.Peer ReviewedPostprint (published version

Exploration of intercell wireless millimeter-wave communication in the landscape of intelligent metasurfaces

Software-defined metasurfaces are electromagnetically ultra-thin, artificial components thatcan provide engineered and externally controllable functionalities. The control over these functionalities isenabled by the metasurface tunability, which is implemented by embedded electronic circuits that modifylocally the surface resistance and reactance. Integrating controllers within the metasurface able them tointercommunicate and adaptively reconfigure, thus imparting a desired electromagnetic operation, opens thepath towards the creation of an artificially intelligent (AI) fabric where each unit cell can have its own sensing,programmable computing, and actuation facilities. In this work we take a crucial step towards bringing theAI metasurface technology to emerging applications, in particular exploring the wireless mm-wave intercellcommunication capabilities in a software-defined HyperSurface designed for operation in the microwaveregime. We examine three different wireless communication channels within the landscape of the reflectivemetasurface: Firstly, in the layer where the control electronics of the HyperSurface lie, secondly inside adedicated layer enclosed between two metallic plates, and, thirdly, inside the metasurface itself. For each casewe examine the physical implementation of the mm-wave transceiver nodes, we quantify communicationchannel metrics, and we identify complexity vs. performance trade-offs.Peer ReviewedPostprint (published version