Silver Chalcogenide Based Memristor Devices

We have fabricated two-terminal chalcogenide-based devices containing Ge2Se3 and Ag that function as memristors. These devices have been electrically characterized at room temperature using quasi-static DC methods, AC sinusoidal methods, and AC pulse testing methods. In all cases, the devices exhibit memristive behavior

Ion beam effect on Ge-Se chalcogenide glass films: Non-volatile memory array formation, structural changes and device performance

The conductive bridge non-volatile memory technology is an emerging way to replace traditional charge based memory devices for future neural networks and configurable logic applications. An array of the memory devices that fulfills logic operations must be developed for implementing such architectures. A scheme to fabricate these arrays, using ion bombardment through a mask, has been suggested and advanced by us. Performance of the memory devices is studied, based on the formation of vias and damage accumulation due to the interactions of Ar+ ions with GexSe1-x (x=0.2, 0.3 and 0.4) chalcogenide glasses as a function of the ion energy and dose dependence. Blanket films and devices were created to study the structural changes, surface roughness, and device performance. Raman Spectroscopy, Atomic Force Microscopy (AFM), Energy Dispersive X-Ray Spectroscopy (EDS) and electrical measurements expound the Ar+ ions behavior on thin films of GexSe1-x system. Raman studies show that there is a decrease in area ratio between edge-shared to corner-shared structural units, revealing occurrence of structural reorganization within the system as a result of ion/film interaction. AFM results demonstrate a tendency in surface roughness improvement with increased Ge concentration, after ion bombardment. EDS results reveal a compositional change in the vias, with a clear tendency of greater interaction between ions and the Ge atoms, as evidenced by greater compositional changes in the Ge rich films

Implementation of binary stochastic STDP learning using chalcogenide-based memristive devices

The emergence of nano-scale memristive devices encouraged many different research areas to exploit their use in multiple applications. One of the proposed applications was to implement synaptic connections in bio-inspired neuromorphic systems. Large-scale neuromorphic hardware platforms are being developed with increasing number of neurons and synapses, having a critical bottleneck in the online learning capabilities. Spike-timing-dependent plasticity (STDP) is a widely used learning mechanism inspired by biology which updates the synaptic weight as a function of the temporal correlation between pre- and post-synaptic spikes. In this work, we demonstrate experimentally that binary stochastic STDP learning can be obtained from a memristor when the appropriate pulses are applied at both sides of the device

Self-Directed Channel Memristor for High Temperature Operation

Ion-conducting memristors comprised of the layered chalcogenide materials Ge2Se3/SnSe/Ag are described. The memristor, termed a self-directed channel (SDC) device, can be classified as a generic memristor and can tolerate continuous high temperature operation (at least 150 °C). Unlike other chalcogenide-based ion conducting device types, the SDC device does not require complicated fabrication steps, such as photodoping or thermal annealing, making these devices faster and more reliable to fabricate. Device pulsed response shows fast state switching in the 10−9 s range. Device cycling at both room temperature and 140 °C show write endurance of at least 1 billion

Low-Cost Test and Characterization Platform for Memristors

The electrical Testing and Characterization of the devices built under research conditions on silicon wafers, diced wafers, or package parts have hampered research since the beginning of integrated circuits. The challenges of performing electrical characterization on devices are to acquire useful and accurate data, the ease of use of the test platform, the portability of the test equipment, the ability to automate quickly, to allow modifications to the platform, the ability to change the configuration of the Device Under Test (DUT) or the Memristor Based Design (MBD), and to do this within budget. The devices that this research is focused on are memristors with unique test challenges. Some of the tests performed on memristors are Voltage sweeps, pulsing of Voltages, and threshold Voltages. Standard methods of testing memristors usually require hands-on experience, multiple bulky work stations, and hours of training. This work reports a novel, low-cost, portable test and characterization platform for many types of memristors with a voltage range from -10V to +10V, which is portable, low-cost, built with off-the-shelf components, and with configurability through software and hardware. To demonstrate the performance of the platform, the platform was able to take a virgin memristor from “forming” to operation voltages, and then incrementally change resistances by Voltage Pulsing. The platform within this work allows the researcher flexibility in electrical characterization by being able to accept many memristor types and MBDs, and applying environmental conditions to the MBD, with this flexibility of the platform the productivity of the researcher will increase

Energy-Efficient STDP-Based Learning Circuits with Memristor Synapses

It is now accepted that the traditional von Neumann architecture, with processor and memory separation, is ill suited to process parallel data streams which a mammalian brain can efficiently handle. Moreover, researchers now envision computing architectures which enable cognitive processing of massive amounts of data by identifying spatio-temporal relationships in real-time and solving complex pattern recognition problems. Memristor cross-point arrays, integrated with standard CMOS technology, are expected to result in massively parallel and low-power Neuromorphic computing architectures. Recently, significant progress has been made in spiking neural networks (SNN) which emulate data processing in the cortical brain. These architectures comprise of a dense network of neurons and the synapses formed between the axons and dendrites. Further, unsupervised or supervised competitive learning schemes are being investigated for global training of the network. In contrast to a software implementation, hardware realization of these networks requires massive circuit overhead for addressing and individually updating network weights. Instead, we employ bio-inspired learning rules such as the spike-timing-dependent plasticity (STDP) to efficiently update the network weights locally. To realize SNNs on a chip, we propose to use densely integrating mixed-signal integrate-andfire neurons (IFNs) and cross-point arrays of memristors in back-end-of-the-line (BEOL) of CMOS chips. Novel IFN circuits have been designed to drive memristive synapses in parallel while maintaining overall power efficiency (/spike/synapse), even at spike rate greater than 10 MHz. We present circuit design details and simulation results of the IFN with memristor synapses, its response to incoming spike trains and STDP learning characterization

Design of Neuromemristive Systems for Visual Information Processing

Neuromemristive systems (NMSs) are brain-inspired, adaptive computer architectures based on emerging resistive memory technology (memristors). NMSs adopt a mixed-signal design approach with closely-coupled memory and processing, resulting in high area and energy efficiencies. Previous work suggests that NMSs could even supplant conventional architectures in niche application domains such as visual information processing. However, given the infancy of the field, there are still several obstacles impeding the transition of these systems from theory to practice. This dissertation advances the state of NMS research by addressing open design problems spanning circuit, architecture, and system levels. Novel synapse, neuron, and plasticity circuits are designed to reduce NMSs’ area and power consumption by using current-mode design techniques and exploiting device variability. Circuits are designed in a 45 nm CMOS process with memristor models based on multilevel (W/Ag-chalcogenide/W) and bistable (Ag/GeS2/W) device data. Higher-level behavioral, power, area, and variability models are ported into MATLAB to accelerate the overall simulation time. The circuits designed in this work are integrated into neural network architectures for visual information processing tasks, including feature detection, clustering, and classification. Networks in the NMSs are trained with novel stochastic learning algorithms that achieve 3.5 reduction in circuit area, reduced design complexity, and exhibit similar convergence properties compared to the least-mean-squares algorithm. This work also examines the effects of device-level variations on NMS performance, which has received limited attention in previous work. The impact of device variations is reduced with a partial on-chip training methodology that enables NMSs to be configured with relatively sophisticated algorithms (e.g. resilient backpropagation), while maximizing their area-accuracy tradeoff