4 research outputs found
Instruction history management for high-performance microprocessors
textHistory-driven dynamic optimization is an important factor in improving
instruction throughput in future high-performance microprocessors. Historybased
techniques have the ability to improve instruction-level parallelism by
breaking program dependencies, eliminating long-latency microarchitecture
operations, and improving prioritization within the microarchitecture. However,
a combination of factors, such as wider issue widths, smaller transistors,
larger die area, and increasing clock frequency, has led to microprocessors that
are sensitive to both wire delays and energy consumption. In this environment,
the global structures and long-distance communications that characterize current
history data management are limiting instruction throughput.
This dissertation proposes the ScatterFlow Framework for Instruction
History Management. Execution history management tasks, such as history
data storage, access, distribution, collection, and modification, are partitioned
and dispersed throughout the instruction execution pipeline. History data
packets are then associated with active instructions and flow with the instructions
as they execute, encountering the history management tasks along the
way. Between dynamic instances of the instructions, the history data packets
reside in trace-based history storage that is synchronized with the instruction
trace cache. Compared to traditional history data management, this ScatterFlow
method improves instruction coverage, increases history data access
bandwidth, shortens communication distances, improves history data accuracy
in many cases, and decreases the effective history data access time.
A comparison of general history management effectiveness between the
ScatterFlow Framework and traditional hardware tables shows that the ScatterFlow
Framework provides superior history maturity and instruction coverage.
The unique properties that arise due to trace-based history storage and
partitioned history management are analyzed, and novel design enhancements
are presented to increase the usefulness of instruction history data within the
ScatterFlow Framework.
To demonstrate the potential of the proposed framework, specific dynamic
optimization techniques are implemented using the ScatterFlow Framework.
These illustrative examples combine the history capture advantages
with the access latency improvements while exhibiting desirable dynamic energy
consumption properties. Compared to a traditional table-based predictor,
performing ScatterFlow value prediction improves execution time and reduces
dynamic energy consumption. In other detailed examples, ScatterFlowenabled
cluster assignment demonstrates improved execution time over previous
cluster assignment schemes, and ScatterFlow instruction-level profiling
detects more useful execution traits than traditional fixed-size and infinite-size
hardware tables.Electrical and Computer Engineerin
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CMOS Compatible Thin-Film ALD Tungsten Nanoelectromechanical Devices
This research focuses on the development of a novel, low-temperature, CMOS compatible, atomic-layer-deposition (ALD) enabled NEMS fabrication process for the development of ALD Tungsten (WALD) NEMS devices. The devices are intended for use in CMOS/NEMS hybrid systems, and NEMS based micro-processors/controllers capable of reliable operation in harsh environments not accessible to standard CMOS technologies. The majority of NEMS switches/devices to date have been based on carbon-nano-tube (CNT) designs. The devices consume little power during actuation, and as expected, have demonstrated actuation voltages much smaller than MEMS switches. Unfortunately, NEMS CNT switches are not typically CMOS integrable due to the high temperatures required for their growth, and their fabrication typically results in extremely low and unpredictable yields. Thin-film NEMS devices offer great advantages over reported CNT devices for several reasons, including: higher fabrication yields, low-temperature (CMOS compatible) deposition techniques like ALD, and increased control over design parameters/device performance metrics, i.e., device geometry. Furthermore, top-down, thin-film, nano-fabrication techniques are better capable of producing complicated device geometries than CNT based processes, enabling the design and development of multi-terminal switches well-suited for low-power hybrid NEMS/CMOS systems as well as electromechanical transistors and logic devices for use in temperature/radiation hard computing architectures. In this work several novel, low-temperature, CMOS compatible fabrication technologies, employing WALD as a structural layer for MEMS or NEMS devices, were developed. The technologies developed are top-down nano-scale fabrication processes based on traditional micro-machining techniques commonly used in the fabrication of MEMS devices. Using these processes a variety of novel WALD NEMS devices have been successfully fabricated and characterized. Using two different WALD fabrication technologies two generations of 2-terminal WALD NEMS switches have been developed. These devices have functional gap heights of 30-50 nm, and actuation voltages typically ranging from 3-5 Volts. Via the extension of a two terminal WALD technology novel 3-terminal WALD NEMS devices were developed. These devices have actuation voltages ranging from 1.5-3 Volts, reliabilities in excess of 2 million cycles, and have been designed to be the fundamental building blocks for WALD NEMS complementary inverters. Through the development of these devices several advancements in the modeling and design of thin-_lm NEMS devices were achieved. A new model was developed to better characterize pre-actuation currents commonly measured for NEMS switches with nano-scale gate-to-source gap heights. The developed model is an extension of the standard field-emission model and considers the electromechanical response, and electric field effects specific to thin-film NEMS switches. Finally, a multi-physics FEM/FD based model was developed to simulate the dynamic behavior of 2 or 3-terminal electrostatically actuated devices whose electrostatic domains have an aspect ratio on the order of 103. The model uses a faux-Lagrangian finite difference method to solve Laplaces equation in a quasi-statatically deforming domain. This model allows for the numerical characterization and design of thin- _lm NEMS devices not feasible using typical non-specialized BEM/FEM based software. Using this model several novel and feasible designs for fixed-fixed 3-terminal WALD NEMS switches capable for the construction of complementary inverters were discovered