2 research outputs found
Enabling Technologies for 3D ICs: TSV Modeling and Analysis
Through silicon via (TSV) based three-dimensional (3D) integrated circuit (IC) aims to stack and interconnect dies or wafers vertically. This emerging technology offers a promising near-term solution for further miniaturization and the performance improvement of electronic systems and follows a more than Moore strategy. Along with the need for low-cost and high-yield process technology, the successful application of TSV technology requires further optimization of the TSV electrical modeling and design. In the millimeter wave (mmW) frequency range, the root mean square (rms) height of the TSV sidewall roughness is comparable to the skin depth and hence becomes a critical factor for TSV modeling and analysis. The impact of TSV sidewall roughness on electrical performance, such as the loss and impedance alteration in the mmW frequency range, is examined and analyzed following the second order small perturbation method. Then, an accurate and efficient electrical model for TSVs has been proposed considering the TSV sidewall roughness effect, the skin effect, and the metal oxide semiconductor (MOS) effect. However, the emerging application of 3D integration involves an advanced bio-inspired computing system which is currently experiencing an explosion of interest. In neuromorphic computing, the high density membrane capacitor plays a key role in the synaptic signaling process, especially in a spike firing analog implementation of neurons. We proposed a novel 3D neuromorphic design architecture in which the redundant and dummy TSVs are reconfigured as membrane capacitors. This modification has been achieved by taking advantage of the metal insulator semiconductor (MIS) structure along the sidewall, strategically engineering the fixed oxide charges in depletion region surrounding the TSVs, and the addition of oxide layer around the bump without changing any process technology. Without increasing the circuit area, these reconfiguration of TSVs can result in substantial power consumption reduction and a significant boost to chip performance and efficiency. Also, depending on the availability of the TSVs, we proposed a novel CAD framework for TSV assignments based on the force-directed optimization and linear perturbation
Integrating simultaneous bi-direction signalling in the test fabric of 3D stacked integrated circuits.
Jennions, Ian K. - Associate SupervisorThe world has seen significant advancements in electronic devices’ capabilities,
most notably the ability to embed ultra-large-scale functionalities in lightweight,
area and power-efficient devices. There has been an enormous push towards
quality and reliability in consumer electronics that have become an indispensable
part of human life. Consequently, the tests conducted on these devices at the
final stages before these are shipped out to the customers have a very high
significance in the research community. However, researchers have always
struggled to find a balance between the test time (hence the test cost) and the
test overheads; unfortunately, these two are inversely proportional.
On the other hand, the ever-increasing demand for more powerful and compact
devices is now facing a new challenge. Historically, with the advancements in
manufacturing technology, electronic devices witnessed miniaturizing at an
exponential pace, as predicted by Moore’s law. However, further geometric or
effective 2D scaling seems complicated due to performance and power concerns
with smaller technology nodes. One promising way forward is by forming 3D
Stacked Integrated Circuits (SICs), in which the individual dies are stacked
vertically and interconnected using Through Silicon Vias (TSVs) before being
packaged as a single chip. This allows more functionality to be embedded with a
reduced footprint and addresses another critical problem being observed in 2D
designs: increasingly long interconnects and latency issues. However, as more
and more functionality is embedded into a small area, it becomes increasingly
challenging to access the internal states (to observe or control) after the device
is fabricated, which is essential for testing. This access is restricted by the limited
number of Chip Terminals (IC pins and the vertical Through Silicon Vias) that a
chip could be fitted with, the power consumption concerns, and the chip area
overheads that could be allocated for testing.
This research investigates Simultaneous Bi-Directional Signaling (SBS) for use
in Test Access Mechanism (TAM) designs in 3D SICs. SBS enables chip
terminals to simultaneously send and receive test vectors on a single Chip
Terminal (CT), effectively doubling the per-pin efficiency, which could be
translated into additional test channels for test time reduction or Chip Terminal
reduction for resource efficiency. The research shows that SBS-based test
access methods have significant potential in reducing test times and/or test
resources compared to traditional approaches, thereby opening up new avenues
towards cost-effectiveness and reliability of future electronics.PhD in Manufacturin