BLITZEN: A highly integrated massively parallel machine

The architecture and VLSI design of a new massively parallel processing array chip are described. The BLITZEN processing element array chip, which contains 1.1 million transistors, serves as the basis for a highly integrated, miniaturized, high-performance, massively parallel machine that is currently under development. Each processing element has 1K bits of static RAM and performs bit-serial processing with functional elements for arithmetic, logic, and shifting

Algorithms for solving large sparse systems of simultaneous linear equations on vector processors

Very efficient algorithms for solving large sparse systems of simultaneous linear equations have been developed for serial processing computers. These involve a reordering of matrix rows and columns in order to obtain a near triangular pattern of nonzero elements. Then an LU factorization is developed to represent the matrix inverse in terms of a sequence of elementary Gaussian eliminations, or pivots. In this paper it is shown how these algorithms are adapted for efficient implementation on vector processors. Results obtained on the CYBER 200 Model 205 are presented for a series of large test problems which show the comparative advantages of the triangularization and vector processing algorithms

Implementation of ILLIAC 4 algorithms for multispectral image interpretation

Research has focused on the design and partial implementation of a comprehensive ILLIAC software system for computer-assisted interpretation of multispectral earth resources data such as that now collected by the Earth Resources Technology Satellite. Research suggests generally that the ILLIAC 4 should be as much as two orders of magnitude more cost effective than serial processing computers for digital interpretation of ERTS imagery via multivariate statistical classification techniques. The potential of the ARPA Network as a mechanism for interfacing geographically-dispersed users to an ILLIAC 4 image processing facility is discussed

Optimasi Algoritma K-Means Clustering dengan Parallel Processing menggunakan Framework R

Parallel processing sering digunakan untuk melakukan optimasi execution time terhadap algoritma data mining. Pada penelitian ini, parallel processing digunakan untuk melakukan optimasi pada algoritma clustering K-Means. Implementasi algoritma K-means dilakukan dengan memanfaatkan package yang tersedia pada framework R. Algoritma K-Means dijalankan secara serial dan parallel. Untuk mendapatkan persentase optimasi, maka dilakukan perbandingan antara execution time pada parallel processing dan execution time pada serial processing. Penelitian ini menggunakan dataset Boston Housing yang umum digunakan pada data mining. Skenario pengujian dibedakan berdasarkan jumlah core dan jumlah centroid. Hasil pengujian menunjukkan bahwa parallel processing untuk tiap skenario memiliki execution time yang lebih kecil daripada serial processing. Optimasi yang dihasilkan cukup signifikan, yakni bernilai 20% hingga 52%. Optimasi tertinggi didapatkan pada jumlah core terbanyak dan jumlah centroid terbesar

A framework for explaining serial processing and sequence execution strategies

Behavioral research produced many task-specific cognitive models that do not say much about the underlying information processing architecture. Such an architecture is badly needed to understand better how cognitive neuroscience can benefit from existing cognitive models. This problem is especially pertinent in the domain of sequential behavior where behavioral research suggests a diversity of cognitive processes, processing modes and representations. Inspired by decades of reaction time (RT) research with the Additive Factors Method, the Psychological Refractory Period paradigm, and the Discrete Sequence Production task, we propose the Cognitive framework for Sequential Motor Behavior (C-SMB). We argue that C-SMB accounts for cognitive models developed for a range of sequential motor tasks (like those proposed by Keele et al., 2003; Rosenbaum et al., 1983, 1986, 1995; Schmidt, 1975; Sternberg et al., 1978, 1988). C-SMB postulates that sequence execution is controlled by a central processor using central-symbolic representations, and a motor processor using sequence-specific motor representations. On the basis of this framework we present a classification of the strategies to produce movement sequences. We complete this presentation by proposing the neural underpinnings of this framework

Neural Pattern Recognition on Multichannel Input Representation

This article presents a new neural pattern recognition architecture on multichannel data representation. The architecture emploies generalized ART modules as building blocks to construct a supervised learning system generating recognition codes on channels dynamically selected in context using serial and parallel match trackings led by inter-ART vigilance signals.Sharp Corporation, Information Techology Research Laboratories, Nara, Japa

A smart environment for biometric capture

The development of large scale biometric systems require experiments to be performed on large amounts of data. Existing capture systems are designed for fixed experiments and are not easily scalable. In this scenario even the addition of extra data is difficult. We developed a prototype biometric tunnel for the capture of non-contact biometrics. It is self contained and autonomous. Such a configuration is ideal for building access or deployment in secure environments. The tunnel captures cropped images of the subject's face and performs a 3D reconstruction of the person's motion which is used to extract gait information. Interaction between the various parts of the system is performed via the use of an agent framework. The design of this system is a trade-off between parallel and serial processing due to various hardware bottlenecks. When tested on a small population the extracted features have been shown to be potent for recognition. We currently achieve a moderate throughput of approximate 15 subjects an hour and hope to improve this in the future as the prototype becomes more complete