BioScript: programming safe chemistry on laboratories-on-a-chip

This paper introduces BioScript, a domain-specific language (DSL) for programmable biochemistry which executes on emerging microfluidic platforms. The goal of this research is to provide a simple, intuitive, and type-safe DSL that is accessible to life science practitioners. The novel feature of the language is its syntax, which aims to optimize human readability; the technical contributions of the paper include the BioScript type system and relevant portions of its compiler. The type system ensures that certain types of errors, specific to biochemistry, do not occur, including the interaction of chemicals that may be unsafe. The compiler includes novel optimizations that place biochemical operations to execute concurrently on a spatial 2D array platform on the granularity of a control flow graph, as opposed to individual basic blocks. Results are obtained using both a cycle-accurate microfluidic simulator and a software interface to a real-world platform

Directed Placement for mVLSI Devices

Continuous-flow microfluidic devices based on integrated channel networks are becoming increasingly prevalent in research in the biological sciences. At present, these devices are physically laid out by hand by domain experts who understand both the underlying technology and the biological functions that will execute on fabricated devices. The lack of a design science that is specific to microfluidic technology creates a substantial barrier to entry. To address this concern, this article introduces Directed Placement, a physical design algorithm that leverages the natural "directedness" in most modern microfluidic designs: fluid enters at designated inputs, flows through a linear or tree-based network of channels and fluidic components, and exits the device at dedicated outputs. Directed placement creates physical layouts that share many principle similarities to those created by domain experts. Directed placement allows components to be placed closer to their neighbors compared to existing layout algorithms based on planar graph embedding or simulated annealing, leading to an average reduction in laid-out fluid channel length of 91% while improving area utilization by 8% on average. Directed placement is compatible with both passive and active microfluidic devices and is compatible with a variety of mainstream manufacturing technologies

Transport or Store? Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage

Flow-based microfluidic biochips have attracted much atten- tion in the EDA community due to their miniaturized size and execution efficiency. Previous research, however, still follows the traditional computing model with a dedicated storage unit, which actually becomes a bottleneck of the performance of bio- chips. In this paper, we propose the first architectural synthe- sis framework considering distributed storage constructed tem- porarily from transportation channels to cache fluid samples. Since distributed storage can be accessed more efficiently than a dedicated storage unit and channels can switch between the roles of transportation and storage easily, biochips with this dis- tributed computing architecture can achieve a higher execution efficiency even with fewer resources. Experimental results con- firm that the execution efficiency of a bioassay can be improved by up to 28% while the number of valves in the biochip can be reduced effectively.Comment: ACM/IEEE Design Automation Conference (DAC), June 201

Placement and routing for cross-referencing digital microfluidic biochips.

Xiao, Zigang."October 2010."Thesis (M.Phil.)--Chinese University of Hong Kong, 2011.Includes bibliographical references (leaves 62-66).Abstracts in English and Chinese.Abstract --- p.iAcknowledgement --- p.viChapter 1 --- Introduction --- p.1Chapter 1.1 --- Microfluidic Technology --- p.2Chapter 1.1.1 --- Continuous Flow Microfluidic System --- p.2Chapter 1.1.2 --- Digital Microfluidic System --- p.2Chapter 1.2 --- Pin-Constrained Biochips --- p.4Chapter 1.2.1 --- Droplet-Trace-Based Array Partitioning Method --- p.5Chapter 1.2.2 --- Broadcast-addressing Method --- p.5Chapter 1.2.3 --- Cross-Referencing Method --- p.6Chapter 1.2.3.1 --- Electrode Interference in Cross-Referencing Biochips --- p.7Chapter 1.3 --- Computer-Aided Design Techniques for Biochip --- p.8Chapter 1.4 --- Placement Problem in Biochips --- p.8Chapter 1.5 --- Droplet Routing Problem in Cross-Referencing Biochips --- p.11Chapter 1.6 --- Our Contributions --- p.14Chapter 1.7 --- Thesis Organization --- p.15Chapter 2 --- Literature Review --- p.16Chapter 2.1 --- Introduction --- p.16Chapter 2.2 --- Previous Works on Placement --- p.17Chapter 2.2.1 --- Basic Simulated Annealing --- p.17Chapter 2.2.2 --- Unified Synthesis Approach --- p.18Chapter 2.2.3 --- Droplet-Routing-Aware Unified Synthesis Approach --- p.19Chapter 2.2.4 --- Simulated Annealing Using T-tree Representation --- p.20Chapter 2.3 --- Previous Works on Routing --- p.21Chapter 2.3.1 --- Direct-Addressing Droplet Routing --- p.22Chapter 2.3.1.1 --- A* Search Method --- p.22Chapter 2.3.1.2 --- Open Shortest Path First Method --- p.23Chapter 2.3.1.3 --- A Two Phase Algorithm --- p.24Chapter 2.3.1.4 --- Network-Flow Based Method --- p.25Chapter 2.3.1.5 --- Bypassibility and Concession Method --- p.26Chapter 2.3.2 --- Cross-Referencing Droplet Routing --- p.28Chapter 2.3.2.1 --- Graph Coloring Method --- p.28Chapter 2.3.2.2 --- Clique Partitioning Method --- p.30Chapter 2.3.2.3 --- Progressive-ILP Method --- p.31Chapter 2.4 --- Conclusion --- p.32Chapter 3 --- CrossRouter for Cross-Referencing Biochip --- p.33Chapter 3.1 --- Introduction --- p.33Chapter 3.2 --- Problem Formulation --- p.34Chapter 3.3 --- Overview of Our Method --- p.35Chapter 3.4 --- Net Order Computation --- p.35Chapter 3.5 --- Propagation Stage --- p.36Chapter 3.5.1 --- Fluidic Constraint Check --- p.38Chapter 3.5.2 --- Electrode Constraint Check --- p.38Chapter 3.5.3 --- Handling 3-pin net --- p.44Chapter 3.5.4 --- Waste Reservoir --- p.45Chapter 3.6 --- Backtracking Stage --- p.45Chapter 3.7 --- Rip-up and Re-route Nets --- p.45Chapter 3.8 --- Experimental Results --- p.46Chapter 3.9 --- Conclusion --- p.47Chapter 4 --- Placement in Cross-Referencing Biochip --- p.49Chapter 4.1 --- Introduction --- p.49Chapter 4.2 --- Problem Formulation --- p.50Chapter 4.3 --- Overview of the method --- p.50Chapter 4.4 --- Dispenser and Reservoir Location Generation --- p.51Chapter 4.5 --- Solving Placement Problem Using ILP --- p.51Chapter 4.5.1 --- Constraints --- p.53Chapter 4.5.1.1 --- Validity of modules --- p.53Chapter 4.5.1.2 --- Non-overlapping and separation of Modules --- p.53Chapter 4.5.1.3 --- Droplet-Routing length constraint --- p.54Chapter 4.5.1.4 --- Optical detector resource constraint --- p.55Chapter 4.5.2 --- Objective --- p.55Chapter 4.5.3 --- Problem Partition --- p.56Chapter 4.6 --- Pin Assignment --- p.56Chapter 4.7 --- Experimental Results --- p.57Chapter 4.8 --- Conclusion --- p.59Chapter 5 --- Conclusion --- p.60Bibliography --- p.6

Strategic Optimization Techniques For FRTU Deployment and Chip Physical Design

Combinatorial optimization is a complex engineering subject. Although formulation often depends on the nature of problems that differs from their setup, design, constraints, and implications, establishing a unifying framework is essential. This dissertation investigates the unique features of three important optimization problems that can span from small-scale design automation to large-scale power system planning: (1) Feeder remote terminal unit (FRTU) planning strategy by considering the cybersecurity of secondary distribution network in electrical distribution grid, (2) physical-level synthesis for microfluidic lab-on-a-chip, and (3) discrete gate sizing in very-large-scale integration (VLSI) circuit. First, an optimization technique by cross entropy is proposed to handle FRTU deployment in primary network considering cybersecurity of secondary distribution network. While it is constrained by monetary budget on the number of deployed FRTUs, the proposed algorithm identi?es pivotal locations of a distribution feeder to install the FRTUs in different time horizons. Then, multi-scale optimization techniques are proposed for digital micro?uidic lab-on-a-chip physical level synthesis. The proposed techniques handle the variation-aware lab-on-a-chip placement and routing co-design while satisfying all constraints, and considering contamination and defect. Last, the first fully polynomial time approximation scheme (FPTAS) is proposed for the delay driven discrete gate sizing problem, which explores the theoretical view since the existing works are heuristics with no performance guarantee. The intellectual contribution of the proposed methods establishes a novel paradigm bridging the gaps between professional communities