Limiting intellectual property : the competition interface

PhDThis is a study of legal limits of the exercise of intellectual property, with emphasis on chip designs. In Part One, the focus is on the economics of innovation dynamics and the nature of the social bargain underlying intellectual property. It analyses the function of intellectual property and the structure of protection of chip designs under the US chip law, the IPIC Treaty and the Agreement on TRIPS. It suggests that while protection of intellectual property is designed to promote technical innovation and enhance competition in the public favour, the innovation process is carried out in conditions of increasingly imperfect competition. On these grounds, a point is made to limit the exercise of proprietary rights in the welfare/efficiency perspective. Part Two addresses the treatment of legal limitations. An analysis is made concerning the evolution of the safeguarding provisions on which unauthorised use of copyright and patent in the British legal system relies. These safeguards, structured within the intellectual property law, have gradually been developed to also rely on a resurgent competition legislation, which has been considerably used by OECD countries to order the exercise of proprietary rights. The ability of modem competition law to induce an intellectual property order, and the features of the adjudicatory process of non-voluntary licences over UK patents are also examined. From the findings the emergence of; namely, a safeguarding policy is identified. The conceptualisation of this institutional policy, aiming at efficiency and welfare objectives related to the exercise of proprietary rights, is a central theme. It shows that safeguarding provisions intrinsic to intellectual property law is insufficient to pursue these objectives, and holds that to protect intellectual property without an effective control of anti-competitive practices is a distorting and unsustainable legal policy

Integration Of Functional Oxides With The Semiconductor Zinc Oxide.

Ferroelectric/semiconductor heterostructures are desirable for multifunctional devices using the charge of a ferroelectric material to manipulate the conductivity of a semi- conductor. The quality of the ferroelectric/semiconductor interface is critical for maintaining a significant ferroelectric polarization charge density, and coupling this charge density into the semiconductor. Therefore, materials must have excellent compatibility. The semiconductor ZnO is a promising can- didate for integration with ferroelectric oxides, due to its excellent structural and chemical compatibility with such materials. This report discusses the thin film growth of select ferroelectric and semiconductor materials, the fabrication of heterostructures and basic capacitor devices using such materials, and the characterization of structural and electrical properties thereof. Pulsed laser deposition (PLD) and molecular beam epitaxy (MBE) are used to ob- tain thin films of desired materials. Standard lithographic methods were used to pattern the materials and to deposit electrical contacts for subsequent testing. Polycrystalline thin films of Pb(Zr,Ti)O3 (PZT) were achieved through solution pro- cessing, and they exhibited ferroelectric behavior in polarization-electric field and capacitance-voltage measurements. Single crystal substrates of ferroelectric LiNbO3 (LN) were purchased in bulk form. Weak c-plane preferential orientation of ZnO thin films was achieved using PLD on PZT films. Highly preferentially oriented c-plane ZnO films were obtained by PLD on LN substrates. Ferroelectric/ZnO heterostructures using PZT and LN as prototype ferroelectric ma- terials were studied. Pt/PZT/ZnO capacitors showed a memory window of 2V in capacitance-voltage and AC conductance measurements. An RLC circuit constructed using the PZT/ZnO capacitor shows a resonant peak shift of 30kHz, which is consis- tent with the expected change in capacitance with switching ferroelectric polarization. LiNbO3 /ZnO heterostructures show evidence of carrier concentration modulation in the semiconductor attributed to the ferroelectric polarization charge. Hall effect mea- surements revealed an order of magnitude reduction in carrier concentration in the ZnO thin film consistent with expected depletion caused by the ferroelectric po- larization charge. The pyroelectric effect in LN substrates was exploited using a basic voltage divider circuit where the change in ZnO conductivity were observed. Upon application of heat, the ferroelectric polarization charge increased, thereby causing further depletion of the ZnO film.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/75978/1/cagin_1.pd

Strategic planning in high-rise construction as a chance for further growth and development of Novi Pazar

Svedoci smo ekonomskog napretka u oblasti visokogradnje na teritoriji Novog Pazara i Tutina u periodu od 2000. pa do danas. Novi Pazar i Tutin su se pre svega kao gradovi odlikovali arhitekturom koja se uglavnom oslanjala na izgradnju kuća kao stambenih mesta za život, međutim sa nedostatkom prostora za dalji rast i širenje gradova, najpre su počele da se grade zgrade od 4-5 spratova, da bi se izmenom gradskih uredbi 2015 i 2016. godine, pristupilo i izgradnji višespratnica od 9 i više spratova. Visokogradnja kao sektor zapošljava čitav niz industrijskih grana, od proizvodnje građevinskih materijala, preko prevoza, do radne snage u oblasti izgradnje ali i usluge inženjera različitih struka. Budući da svaka višespratnica predstavlja projekat sa tačno utvrđenim početkom i završetkom, kao takav se mora posmatrati kroz savremene oblike strategijskog planiranja, uvažavajući sve aspekte finansijsko investicione analize ali ostavljajući i prostor za primenu savremenog oblika planiranja

Capacitance Optimization and Ballistic Modeling of Nanowire Transistors

Downscaling of Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs) has contributed to increased microchip device density and to improve the functionality of the electronic circuits. The dimensions of state of art MOSFET is down to a few nanometers. It has been demonstrated that smaller MOSFETs are faster and more energy-efficient. However, with continued device scaling the performance of ICs starts to deteriorate making it important to implement new technology solutions. Nanowire transistors have in recent years been introduce to face some of semiconductor challenges, such as short-channel effects and performance degradation. The geometry of the nanowires allows the gate contact to be wrapped all-around the nanowire which offers an excellent electrostatic integrity. However, the performance of nanowire MOSFETs is restricted due to parasitic capacitances and resistances between the metal contacts and semiconductor nanowires. The presence of parasitic capacitances and resistances in devices introduces time delay, which is the time required for charging and discharging the capacitances. Insulating interlayers with high relative permittivity contribute to higher capacitances, and thereby increased time delay. There are amount of materials with low relative permittivity that are suitable to replace the conventionally used spacer material, SiO2. The high k-value of SiO2 is believed to contribute to higher parasitic capacitances, and performance degradation. Integration of Hydrogen silsesquioxane (HSQ) as an interlayer dielectric in multilevel interconnects has received much attention in semiconductor fabrication. To investigate the possibility of using HSQ as insulating material in nanowire transistors, the properties and the relative permittivity of this material should be explored. Measurement of HSQ k-value has not been done before and this value has only been speculated. Therefore, a parallelplate capacitor structure with a varying HSQ-thickness, obtained by using Electron Beam Lithography (EBL), has been manufactured to study the properties of HSQ. Furthermore, the thickness of HSQ has been estimated and CV - characteristics has been considered to measure the k-value of this material. Experimental measurements on the manufacturedstructure showed that HSQ is durable as a spacer material, and it has the capability to be used as interlayer dielectric in nanowire transistors. Additionally, the calculated relative permittivity, k, of HSQ was approximately 3.00 0.40. Furthermore, this thesis is about investigating the performance of ballistic 1-D MOSFETs at high frequencies, explaining the operational principles of these devices, calculating RF figures of merit, and extracting high frequency transistor metrics, fT and fmax. The simulation in this thesis is based on parameter optimization to find the optimal parameters that give minimized parasitic capacitances and thereby improved transistor performance. To achieve these purposes, 3D-structures have been modeled using COMSOL Multiphysics. The numerical calculations on the modeled 3D nanowire transistor structures demonstratea transition frequency fT = 480 GHz and maximum frequency fmax = 1.60 THz.Teknologiutvecklingen inom halvledarindustrin och integrerade krestsar har inom de senaste åren skett i en mycket hög takt, vilket också har medfört en förbättring av transistornas prestanda. Transistorn är grundläggande biståndsdel i elektroniska kretsar med huvudsaklig uppgift att styra strömmar och fungerar på så sätt som ett elektriskt relä. Transistorn består av tre elektroder, som kallas source, drain och gate. Genom att applicera en elektrisk spänning över gate-elektroden, kan resistansen hos kanalen mellan source och drain kontrolleras. På det sättet styrs strömmen genom den elektriska kretsen. Användningsområden för transistorer sträcker sig från förstärkning av elektriska signaler till att bygga logiska kretsar som används för att utföra många, komplexa lösningar. Nedskalning av transistorer till storleksordning av tiotals nanometer har under de senaste 40 åren bidragit till ökad prestanda av integrerade kretsar. Idag är det möjligt att integrera fler transistorer, upp till miljarder, på ett och samma chip. Transistorn baserad på halvledarmaterialet kisel, har varit den dominerande inom industrin. Kisel är ett halvledarmaterial som under flera decennier har varit en enastående kandidat till både digitala och analoga applikationer. Kisel är dock ganska ofördelaktig som en elektisk ledare. De fysikaliska begränsningarna hos det materialet har blivit ett hinder inför en fortsatt nedskalning av transistorer och en fortsatt förbättring av transistorns prestanda. Av denna anledning, utforskas det alltjämt konkurrerande tekniker för att överträffa de existerande kiselbaserade kretslösningarna och för att utveckla nya tekniska lösningar. Forskning och utveckling av transistor baserad på alternativa material och utformningar kan gynna utmaningar vid ytterligare miniatyrisering av transistorer. Ett av alternativen är användande av III-V sammansatta halvledare, främst indiumarsenid InAs eller indiumgalliumarsenid InGaAs. Dessa material har förbättrade egenskaper och kan leda till utveckling av snabba transistor. Detta beror på att elektronerna i dessa material har en hög hastighet i jämförelse med kisel, vilket på sikt bidrar till en transistor med betydligt lägre energiförbrukning. Användning av III-V halvledare har öppnat nya dörrar för att utveckla nya typer av transistorer som är baserade på nanotrådar. Strömflödet genom kanalen kan bättre kontrolleras eftersom dess cylindriska geometri tillåter gate-kontakten, som lätt kan lindras runt tråden, att ha mer precis kontroll över kanalen. Prestandan av den typen av transistor förväntas ligga i terahertz-området, tack vare kombinationen av dessa innovationer. Trots förbättrad tansistorprestanda, står de nya teknikerna inför nya utmaningar. Därför bör nya lösningar utredas för att kunna uppnå ett optimerat resultat. I det här projektet har fysikaliska och ballistiska simuleringar av nanotrådstransistor utförs med syftet att uppskatta prestandan och studera kapacitansernas inverkan. Detta har genomförts genom att variera dimensionerna av den modellerade 3D transistorstrukturen. Dessutom omfattar projektet tillverkning av en platt kondensator som sedan utvärderas. Detta görs i syfte att undersöka möjligheten att ersätta det traditionella isolerande materialet mellan metal elektroderna med andra material som har lägre dielektrik konstant, som till exempel HSQ. På det viset kan man minska påverkan av parasitiska kapacitanser som annars påverkar transistorprestandan negativt