Layout Design and Implementation of Adiabatic based Low Power CPAL Ripple Carry Adder

his paper presents schematic and layout design s for low power adiabatic Ripple Carry Adder which is implemented by proposed N - type & P - type Full Adder Cell . Adiabatic logic Design is the most efficient energy saving technique which provides very low power dis sipat ion for VLSI circuits. In this paper the main emphasis on the most significant technique of adiabatic logic design that is Complementary Pass Transistor Logic. Simulation results show s that energy loss of digital VLSI circuits can be greatly reduced by using Complementary Pass Transistor A diabatic Logic technique. All the circuits have been simulated on BSIM3V3 90nm technology on tanner EDA tool