A statistical study of time dependent reliability degradation of nanoscale MOSFET devices

Charge trapping at the channel interface is a fundamental issue that adversely affects the reliability of metal-oxide semiconductor field effect transistor (MOSFET) devices. This effect represents a new source of statistical variability as these devices enter the nano-scale era. Recently, charge trapping has been identified as the dominant phenomenon leading to both random telegraph noise (RTN) and bias temperature instabilities (BTI). Thus, understanding the interplay between reliability and statistical variability in scaled transistors is essential to the implementation of a ‘reliability-aware’ complementary metal oxide semiconductor (CMOS) circuit design. In order to investigate statistical reliability issues, a methodology based on a simulation flow has been developed in this thesis that allows a comprehensive and multi-scale study of charge-trapping phenomena and their impact on transistor and circuit performance. The proposed methodology is accomplished by using the Gold Standard Simulations (GSS) technology computer-aided design (TCAD)-based design tool chain co-optimization (DTCO) tool chain. The 70 nm bulk IMEC MOSFET and the 22 nm Intel fin-shape field effect transistor (FinFET) have been selected as targeted devices. The simulation flow starts by calibrating the device TCAD simulation decks against experimental measurements. This initial phase allows the identification of the physical structure and the doping distributions in the vertical and lateral directions based on the modulation in the inversion layer’s depth as well as the modulation of short channel effects. The calibration is further refined by taking into account statistical variability to match the statistical distributions of the transistors’ figures of merit obtained by measurements. The TCAD simulation investigation of RTN and BTI phenomena is then carried out in the presence of several sources of statistical variability. The study extends further to circuit simulation level by extracting compact models from the statistical TCAD simulation results. These compact models are collected in libraries, which are then utilised to investigate the impact of the BTI phenomenon, and its interaction with statistical variability, in a six transistor-static random access memory (6T-SRAM) cell. At the circuit level figures of merit, such as the static noise margin (SNM), and their statistical distributions are evaluated. The focus of this thesis is to highlight the importance of accounting for the interaction between statistical variability and statistical reliability in the simulation of advanced CMOS devices and circuits, in order to maintain predictivity and obtain a quantitative agreement with a measured data. The main findings of this thesis can be summarised by the following points: Based on the analysis of the results, the dispersions of VT and ΔVT indicate that a change in device technology must be considered, from the planar MOSFET platform to a new device architecture such as FinFET or SOI. This result is due to the interplay between a single trap charge and statistical variability, which has a significant impact on device operation and intrinsic parameters as transistor dimensions shrink further. The ageing process of transistors can be captured by using the trapped charge density at the interface and observing the VT shift. Moreover, using statistical analysis one can highlight the extreme transistors and their probable effect on the circuit or system operation. The influence of the passgate (PG) transistor in a 6T-SRAM cell gives a different trend of the mean static noise margin

Hydrogenated amorphous silicon deposited by ECR-CVD for the definition of semiconductors nanowires

Orientador: José Alexandre DinizTese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: Os nanofios semicondutores são primordiais para a obtenção dos atuais e futuros dispositivos ele-trônicos (transistores) e circuitos integrados (microprocessadores), que exigem tecnologias com dimensões menores que 50 nm e 10 nm, respectivamente. Nesse contexto, esse trabalho desenvol-veu métodos alternativos para a definição de nanofios semicondutores (silício e arseneto de gálio (III-V)), tendo como base filmes de silício amorfo hidrogenado (Si-a:H) depositado por ECR-CVD (Electron Cyclotron Resonance (ECR) - Chemical Vapor Deposition (CVD)), em tempera-tura ambiente. Assim, foram obtidos: (i) Filmes de Si-a:H depositado por ECR-CVD, em temperatura ambiente, com espessu-ras de 60 e 150 nm; (ii) Nanofios de silício (Silicon Nanowires ¿ SiNWs), que são estruturas tridimensionais (3D) com dimensões críticas menores que 150 nm, sobre substratos de Si e SOI (Sili-con On Insulator) utilizando as técnicas sequenciais de fotolitografia (Photolithogra-phy ¿ PL) e de litografia por espaçador (Spacer Lithography ¿ SL ou Self Aligned Double Pattern - SADP) de filme de Si-a:H. Assim, foram obtidos SiNWs com largu-ras entre 16 nm e 143 nm, com diferentes tipos de camada sacrificial (alumínio (Al), ni-treto de silício (SiNx) e fotorresiste), e foram fabricados dispositivos MOS (Metal-Oxide-Semiconductor) 3D, capacitores e transistores JNTs (Junctionless Nanowire Transistors), que indicaram o bom funcionamento dos SiNWs como canal de condu-ção de corrente elétrica; (iii) SiNWs utilizando as etapas sequenciais de litografias PL, de milling (remoção de ma-terial) com feixe de íons focalizados de gálio (Ga+) (Gallium Focused Ion Beam ¿ FIB Milling (FIB_M)) e de SL (espaçador de filme de Si-a:H). Dessa forma, foram obtidos SiNWs de 35 nm de largura e espaçamento de 170 nm, dimensões estas que podem ser usadas em nós tecnológicos entre 45 e 65 nm; (iv) SiNWs-n+ e III-VNWs-n+ (Nanofios de semicondutores III-V ¿ em inglês, III-V Na-nowires) utilizando a técnica de litografia por feixe de íons focalizados de gálio (Ga+) (Gallium Focused Ion Beam ¿ FIB Lithography (FIB_L)), tendo como máscara o filme de Si-a:H, sobre substratos de Si e de semicondutor III-V. Assim, foram obtidos SiNWs-n+, com larguras entre 245 e 365 nm, e espaçamentos entre 155 nm e 250 nm. Com esses SiNWs-n+, usados como canal de condução de corrente elétrica entre fonte e dreno, foram fabricados transistores pseudo-MOS. Os resultados elétricos indicam que esses nanofios estão funcionando corretamente, pois os transistores apresentam as regiões tríodo e de saturação sendo características de transistores MOS. Além disso, com o processo de FIB_L, foi possível obter III-VNWs-n+ com larguras de 75 nm e 115 nm e espaçamentos entre 350 e 370 nm, respectivamente, que serão usados na fa-bricação de transistores JNTs baseados em semicondutores III-V. Por fim, salienta-se que: (i) o filme de Si-a:H depositado por ECR-CVD, em temperatura ambien-te, utilizado como espaçador para a tecnologia SL (método barato e alternativo na definição dos nanofios), usando diferentes camadas sacrificiais (Al, SiNx e fotorresiste(FR)), e como camada protetora (máscara) nas técnicas FIB_M e FIB_L, são inovações dessa tese, para a obtenção de nanofios semicondutores, pois não foram encontrados trabalhos similares na literatura; (ii) esse trabalho consegue mostrar que os nossos processos são viáveis para a prototipagem de atuais dis-positivos 3D. Portanto, trata-se de um importante resultado, para o desenvolvimento da nanotec-nologia baseada em SiNWs no BrasilAbstract: Semiconductors nanowires are essential for obtaining present and future electronic devices (tran-sistors) and integrated circuits (microprocessors), which require technologies with dimensions smaller than 50 nm and 10 nm, respectively. In this context, this work developed alternative meth-ods for the definition of semiconductors nanowires (silicon and gallium arsenide (III-V)) based on hydrogenated amorphous silicon (a-Si:H) films deposited by ECR-CVD (Electron Cyclotron Reso-nance (ECR) - Chemical Vapor Deposition (CVD) at room temperature. Thus, the obtained results were: (i) a-Si:H films deposited by ECR-CVD, at room temperature, with thicknesses values of 60 and 150 nm; (ii) Silicon nanowires (SiNWs), which are three-dimensional (3D) structures with critical dimensions smaller than 150 nm, on Si and SOI (Silicon On Insulator) substrates were obtained using Photolithography (PL) and Spacer Lithography (SL or Self Aligned Double Pattern - SADP) of a-Si:H film. Like this, SiNWs were obtained with widths be-tween 16 nm and 143 nm, with different types of sacrificial layers (Al, SiNx and photo-resist), and MOS (Metal-Oxide-Semiconductor) 3D devices were fabricated, capacitors and JNTs (Junctionless Nanowire Transistors) transistors, which indicated the good operation of the SiNWs as electrical current conduction channel; (iii) SiNWs were obtained using the sequential steps of PL, milling with Gallium Focused Ion Beam (FIB Milling - FIB_M) and SL (a-Si-:H films as spacer). In this way, SiNWs were obtained with values of width and spacing of 35 nm and 170 nm respectively. These dimensions can be used in technological nodes between 45 and 65 nm; (iv) SiNWs-n+ and III-VNWs-n+ (III-V Nanowires) were obtained using the Gallium Fo-cused Ion Beam Lithography (FIB Lithography - FIB_L) technique, with mask of the a-Si:H film mask, on Si and III-V semiconductor substrates. Thus, SiNWs-n+ were fabri-cated with widths between 245 and 365 nm, and spacings between 155 nm and 250 nm. With these SiNWs-n+, which were used as the channel of electrical current conduc-tion between source and drain, pseudo-MOS transistors were fabricated the extracted. Electrical results indicate that these nanowires are working correctly. In addition, with the FIB_L process, it was possible to obtain III-VNWs-n+ with widths of 75 nm and 115 nm and spacings of 350 and 370 nm, respectively. These III-VNWs-n+ will be used in the fabrication of JNTs transistors. Finally, it is important to mention that: (i) the a-Si:H film deposited by ECR-CVD, at room tem-perature, used as a spacer for SL technology (alternative and cheaper method for the nanowires definition), using different sacrificial layers (Al, SiNx and photoresist), and as protective layer (mask) in the FIB_M and FIB_L techniques, are innovations of this thesis, to obtain semiconduc-tors nanowires, because similar works were not found in literature; (ii) this work suggests that our processes are feasible for a prototyping of novel 3D devices. Therefore, there are important result in this thesis for the development of nanoelectronics in BrazilDoutoradoEletrônica, Microeletrônica e OptoeletrônicaDoutora em Engenharia ElétricaCAPE