Comparative Analysis of Cryptography Library in IoT

The paper aims to do a survey along with a comparative analysis of the various cryptography libraries that are applicable in the field of Internet of Things (IoT). The first half of the paper briefly introduces the various cryptography libraries available in the field of cryptography along with a list of all the algorithms contained within the libraries. The second half of the paper deals with cryptography libraries specifically aimed for application in the field of Internet of Things. The various libraries and their performance analysis listed down in this paper are consolidated from various sources with the aim of providing a single comprehensive repository for reference to the various cryptography libraries and the comparative analysis of their features in IoT.Comment: 5 pages, 14 table

Review of the NIST Light-weight Cryptography Finalists

Since 2016, NIST has been assessing lightweight encryption methods, and, in 2022, NIST published the final 10: ASCON, Elephant, GIFT-COFB, Grain128-AEAD, ISAP, Photon-Beetle, Romulus, Sparkle, TinyJambu, and Xoodyak. At the time that the article was written, NISC announced ASCOn as the chosen method that will be published as NIST'S lightweight cryptography standard later in 2023. In this article, we provide a comparison between these methods in terms of energy efficiency, time for encryption, and time for hashing.Comment: 6 page

Performance Evaluation of NIST LWC Finalists on AVR ATmega and ARM Cortex-M3 Microcontrollers

This paper presents results of performance evaluation of NIST Lightweight Cryptography standardization finalists which are implemented by us. Our implementation method puts on the target to reduce RAM consumption on embedded devices. Our target microcontrollers are AVR ATmega 128 and ARM Cortex-M3. We apply our implementation method to five AEAD schemes which include four finalists of the NIST lightweight cryptography standardization and demonstrate the performance evaluation on target microcontrollers. From our performance evaluation of the RAM size, we have achieved 117-byte TinyJAMBU-128 on ATmega 128 and 140-byte TinyJAMBU-128 on ARM Cortex-M3. Our implementation of TinyJAMBU-128 has the smallest RAM of all the target AEAD schemes

Аналіз апаратної підтримки криптографії у пристроях інтернету речей

This article analyzes the features and functionality of embedded cryptographic accelerators in 8/16/32-bit general purpose microcontrollers designed to adapt traditional cryptography to the requirements of IoT-devices. It is established that traditional cryptographic algorithms and protocols used on the Internet in the case of software implementation do not meet the requirements of things related to –devices, the speed, the amount of memory required, and power consumption. The tendencies of development of light weight cryptography and cryptoaccelerators in microcontrollers from the point of view of balance of safety, cost and productivity are shown. The performance gain in the use of cryptographic accelerators for encryption, hashing and generation of random numbers in comparison with optimized software implementations is estimated. In particular, it is noted that the use of cryptographic accelerators allows to raise the speed of AES encryption 10-20 times for 8/16-bit processors and up to 150 times for 32-bit compared with software implementations of the algorithm. The growth of the SHA-1, SHA-256 hash rate algorithms in 32-bit microcontrollers is more than 100 times faster, and the НМАС is approaching 500. This allows 32-bit processors to use traditional cryptographic algorithms and protocols without significant constraints. It has also been shown that 32-bit microcontrollers have a trend towards the implementation of comprehensive security solutions that not only accelerate a wide range of symmetric and asymmetric algorithms and protocols, but also provide the ability to securely store and generate keys, securely download and update code, support digital signatures, and certificates. It is noted that manufacturers of microcontrollers are increasingly forced to pay attention to physical and algorithmic methods of protecting cryptographic accelerators from attacks through side-channels, in the first place attacks of analysis of power consumption, which constitute the main danger to devices of the Internet of things.У даній статті проаналізовано характеристики та функціональні можливості вбудованих криптоакселераторів у 8/16/32-бітових мікроконтролерах загального призначення, покликаних адаптувати традиційну криптографію до вимог пристроїв Інтернету речей. Встановлено, що традиційні криптоалгоритми і протоколи, що застосовуються в мережі Інтернет при програмній реалізації не відповідають вимогам, які ставляться до пристроїв Інтернету речей. Показано тенденції розвитку легковагової криптографії та криптоакселераторів у мікроконтролерах з точки зору балансу безпеки, вартості і продуктивності. Оцінено виграш в продуктивності при застосуванні криптоакселераторів для шифрування, хешування та генерації випадкових чисел у порівнянні з оптимізованими програмними реалізаціями. Звертається увага на методи захисту криптоакселераторів від атак через сторонні канали, у першу чергу атак на енергоспоживання, що становлять головну небезпеку

Vulnerability Analysis of the MAVLink Protocol for Command and Control of Unmanned Aircraft

The MAVLink protocol is an open source, point-to-point networking protocol used to carry telemetry and to command and control many small unmanned aircraft. This research presents three exploits that compromise confidentiality, integrity, and availability vulnerabilities in the communication between an unmanned aerial vehicle and a ground control station using the MAVLink protocol. The attacks assume the configuration settings for the data-link hardware have been obtained. Field experiments using MAVProxy to compromise communication between an ArduPilot Mega 2.5 autopilot and the Mission Planner application demonstrate that all three exploits are successful when MAVLink messages are unprotected. A methodology is proposed to quantify the cost of securing the MAVLink protocol through the measurement of network latency, power consumption, and exploit success. Experimental measurements indicate that the ArduPilot Mega 2.5 autopilot running the ATmega2560 processor at 16 MHz with the standard, unsecured MAVLink protocol consumes on average 0.0105 additional watts of power per second and operates with an average additional latency of 0.11 seconds while under the most resource-intensive attack than when not under attack

Secure Binary Field Multiplication

Binary eld multiplication is the most fundamental building block of binary eld Elliptic Curve Cryptography (ECC) and Galois/Counter Mode (GCM). Both bit-wise scanning and Look-Up Table (LUT) based methods are commonly used for binary eld multiplication. In terms of Side Channel Attack (SCA), bit-wise scanning exploits insecure branch operations which leaks information in a form of timing and power consumption. On the other hands, LUT based method is regarded as a relatively secure approach because LUT access can be conducted in a regular and atomic form. This ensures a constant time solution as well. In this paper, we conduct the SCA on the LUT based binary eld multiplication. The attack exploits the horizontal Correlation Power Analysis (CPA) on weights of LUT. We identify the operand with only a power trace of binary eld multiplication. In order to prevent SCA, we also suggest a mask based binary eld multiplication which ensures a regular and constant time solution without LUT and branch statements

All the Polynomial Multiplication You Need on RISC-V

Polynomial multiplication is a core operation for public key cryptography, such as pre-quantum cryptography (e.g. elliptic curve cryptography) and post-quantum cryptography (e.g. code-based cryptography and multivariate-based cryptography). For this reason, the efficient and secure implementation of polynomial multiplication has been actively conducted for high availability and security level in application services. In this paper, we present all polynomial multiplication methods on modern 32-bit RISC-V processors. We re-designed expensive implementations of polynomial multiplication on legacy microcontrollers (e.g. 8-bit AVR, 16-bit MSP, and 32-bit ARM) for new instruction sets of 32-bit RISC-V processors. Secondly, we suggest the optimal operand length for each polynomial multiplication on 32-bit RISC-V processors. With this implementation technique and Karatsuba algorithm, we achieved scalable features, which ensures the polynomial multiplication in any operand lengths with reasonably fast performance. Third, we propose instruction set extensions for the optimal implementation of polynomial multiplication on 32-bit RISC-V processors. This new feature introduces significant performance enhancements. Lastly, the proposed implementation is a public domain and following researchers can easily re-produce the result

Authenticated Encryption for Very Short Inputs

We study authenticated encryption (AE) modes dedicated to very short messages, which are crucial for Internet-of-things applications. Since the existing general-purpose AE modes need at least three block cipher calls for non-empty messages, we explore the design space for AE modes that use at most two calls. We proposed a family of AE modes, dubbed Manx, that work when the total input length is less than $2n$ bits, using an $n$-bit block cipher. Notably, the second construction of Manx can encrypt almost n-bit plaintext and saves one or two block cipher calls from the standard modes, such as GCM or OCB, keeping the comparable provable security. We also present benchmarks on popular 8/32-bit microprocessors using AES. Our results show the clear advantage of Manx over the previous modes for such short messages

PRISEC: Comparison of Symmetric Key Algorithms for IoT Devices

With the growing number of heterogeneous resource-constrained devices connected to the Internet, it becomes increasingly challenging to secure the privacy and protection of data. Strong but efficient cryptography solutions must be employed to deal with this problem, along with methods to standardize secure communications between these devices. The PRISEC module of the UbiPri middleware has this goal. In this work, we present the performance of the AES (Advanced Encryption Standard), RC6 (Rivest Cipher 6), Twofish, SPECK128, LEA, and ChaCha20-Poly1305 algorithms in Internet of Things (IoT) devices, measuring their execution times, throughput, and power consumption, with the main goal of determining which symmetric key ciphers are best to be applied in PRISEC. We verify that ChaCha20-Poly1305 is a very good option for resource constrained devices, along with the lightweight block ciphers SPECK128 and LEA.info:eu-repo/semantics/publishedVersio