Design considerations for integrated continuous-time chaotic oscillators

This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation using Gm-C integrated circuit techniques. The paper also presents an analysis of the most significant hardware nonidealities of Gm-C circuits on the chaotic operation-the basis to design robust integrated circuits with reproducible and easily controllable behavior. The techniques in the paper are illustrated through a circuit fabricated in 2.4-/iin double-poly technology.Comisión Interministerial de Ciencia y Tecnología TIC 96-1392-CO2-

CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current

Bifurcations and synchronization using an integrated programmable chaotic circuit

This paper presents a CMOS chip which can act as an autonomous stand-alone unit to generate different real-time chaotic behaviors by changing a few external bias currents. In particular, by changing one of these bias currents, the chip provides different examples of a period-doubling route to chaos. We present experimental orbits and attractors, time waveforms and power spectra measured from the chip. By using two chip units, experiments on synchronization can be carried out as well in real-time. Measurements are presented for the following synchronization schemes: linear coupling, drive-response and inverse system. Experimental statistical characterizations associated to these schemes are also presented. We also outline the possible use of the chip for chaotic encryption of audio signals. Finally, for completeness, the paper includes also a brief description of the chip design procedure and its internal circuitry

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

A study of synchronization in chaotic autonomous Ćuk dc/dc converters

Author name used in this publication: H. H. C. IuAuthor name used in this publication: C. K. TseVersion of RecordPublishe

Method and apparatus for hybrid encryption

Described herein is a combination of mixed-signal hardware and software that is capable or realizing hybrid chaotic oscillators that can be tuned digitally. This includes the type/class of chaotic oscillator, initial conditions, nonlinear elements, thresholds, nonlinear event surfaces, delays, etc. At the same time, tunable methods of how to use the chaotic oscillator information to encrypt and decrypt both analog and digital information is presented. This will make the secure information not vulnerable by digital information compromises or hardware breach.Board of Regents, University of Texas Syste

IC design for spread spectrum communication exploiting chaos

This paper presents a 2.4 /spl mu/m CMOS IC prototype which includes a programmable chaotic generator and some interface circuitry for chaotic encryption. It realizes a member of the family of the canonical Chua's state equation. It exhibits several bifurcation parameters by changing a few external bias currents and can be used for the chaotic encryption of audio signals

Experimental verification of chaotic encryption of audio using monolithic chaotic modulators

This paper reports the first experimental verification of chaotic encryption of audio signals using integrated circuits. It is based on a g m-C modulator/demodulator analog CMOS IC that implements a 3rd-order nonlinear differential equation. This has been fabricated in 2.4 micrometer double-poly technology and includes on-chip tuning circuitry based on amplitude detection. It is capable of generating controllable continuous-time chaotic signals. Also, measurements demonstrate how to exploit the synchronization between two of them for encrypted transmission. In these experiments, the worst-case signal to noise ratio of the recovered signal is greater than +40 dB (at the low corner of the audio spectrum) with less than -0.2 dB loss of the input signal power. At higher frequencies, the signal-to-noise ratio rises up to +60 dB, while retaining similar losses at the receiver.European Union ESPRIT IV 879