Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems

Abstract 1 We present an approach to schedulability analysis for the synthesis of multi-cluster distributed embedded systems consisting of timetriggered and event-triggered clusters, interconnected via gateways. We have also proposed a buffer size and worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of our approaches. 1

Design Optimization of Time- and Cost-Constrained Fault-Tolerant Distributed Embedded Systems

Submitted on behalf of EDAA (http://www.edaa.com/)International audienceIn this paper we present an approach to the design optimization of fault-tolerant embedded systems for safety-critical applications. Processes are statically scheduled and communications are performed using the time-triggered protocol. We use process re-execution and replication for tolerating transient faults. Our design optimization approach decides the mapping of processes to processors and the assignment of fault-tolerant policies to processes such that transient faults are tolerated and the timing constraints of the application are satisfied. We present several heuristics which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example

IEE Proceedings: Computers and Digital Techniques Special issue on "Design and Test Conference in Europe", DATE 03

Editorial Special Issue on DATE03 Design and Test in Europe (DATE) is the main European conference that addresses all topics of research into technologies for electronic and embedded systems engineering. This covers design (hardware and embedded software), verification and test, algorithms and tools for design automation of electronic circuits and systems for wireless communications, multimedia and automotive systems. This Special Issue of IEE Proceedings Computers & Digital Techniques presents extended versions of selected papers from the 6th DATE conference held from 3-7 March 2003 in Munich, Germany. From the 152 papers presented, the executive and technical program committees selected 14 papers that received high grades in the review process for inclusion in this special issue. The authors of 12 papers accepted the invitation and submitted extended versions of their manuscript for peer-reviewing. These papers provide a good cross section of topics covered at DATE 03. The first five papers address “design methods”, including reconfigurable computing, power-aware system and circuit level design, asynchronous design, and networks on chip. The sixth, seventh, eighth, ninth and tenth papers address “CAD tools”, including synthesis of distributed embedded systems, transformation-based formal system design, high level synthesis, and interconnect modelling. The final two papers address “test”, including delay testing and low cost SoC test. The 12 papers are summarised in greater detail below. The first paper, Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling, by Mei et al., describes a modulo scheduling algorithm capable of exploiting loop-level parallelism in coarse-grained reconfigurable architectures, and proposes a graph presentation to model coarse-grained architectures. The algorithm is capable of placing, scheduling and routing operations simultaneously in a modulo-constrained 3D space, and it is evaluated using different tested kernels. The second paper, Scheduling and Mapping of Conditional Task Graph for the Synthesis of Low Power Embedded Systems, by Wu et al., addresses energy minimization in data/control dominated distributed embedded systems using dynamic voltage scaling (DVS). Novel DVS and genetic-based mapping techniques are described, and it is shown that a significant reduction in system energy dissipation is possible when compared with approaches that neglect the availability of DVS. The third paper, Masking the Energy Behaviour of DES Encryption”, by Saputra et al., considers the masking of energy consumption of the Data Encryption Standards algorithm by augmenting the instruction set architecture of a 32-bit processor used in smart cards with secure instruction. To support the secure operations, the necessary modifications to the processor architecture and instruction op-codes are outlined. The effectiveness of the augmented approach is demonstrated by simulation and comparison with existing approaches. The fourth paper, Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design, by Madalinski et al., tackles coding conflicts in Signal Transition Graphs (STGs) used for asynchronous control circuit behavior description. A visualization framework is proposed aimed at facilitating the manual refinement of an STG with complete state coding conflicts (i.e. conflicting cores). Two case studies are included to demonstrate the proposed framework. The fifth paper, Trade Offs in the Design of a Router with Both Guaranteed and Best Effort Services for Networks on Chip, by Rijpkema et al., addresses the problem of managing the design of complex chips by decoupling computation and communication. A router-based NoC architecture that combines guaranteed and best-effort services is proposed and a discussion of the important design issues (trade offs between complexity and efficiency) of such a router is presented. A CMOS prototype of the proposed router is also described. The sixth paper, Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems, by Pop et al., addresses the analysis and optimization of heterogeneous time-triggered and event-triggered systems implemented on multi-cluster embedded networks. Optimization heuristics for system synthesis are proposed, and validated using extensive experimental results including a real-life example. The seventh paper, Development and Application of Design Transformations in ForSyDe, by Sander et al., focuses on the development of a formal system design as an effective methodology for complex systems. The methodology is based on transformational design refinement, the formal basis of the transformations is discussed, and the benefits of transformations are illustrated through the design of an eighth-order FIR filter. The eight paper, Behavioural Specification Allocation to Minimize Bit Level Waste of Functional Units, by Molina et al., addresses the problem of hardware waste in high level synthesis, and proposes an allocation algorithm that minimizes this waste. The algorithm efficiency is demonstrated by extensive experimental results and comparative study with a current approach. The ninth paper, Dynamically Increasing the Scope of Code Motions During High-Level Synthesis of Digital Circuits, by Gupta et al., discusses improving the quality of control-intensive (nested conditionals and loops) high-level synthesis results by proposing dynamic conditional branch balancing technique. Two real-life multimedia and image processing applications are presented to demonstrate the effectiveness of the technique. The tenth paper, Modelling and Evaluation of Substrate Noise Induced by Interconnects, by Martorell et al., investigates the importance of interconnects as a source of substrate noise, and proposes a model for noise coupling between integrated signal interconnects and silicon substrate. The model accuracy is checked against real measured data obtained from 0.35?m test structures. The eleventh paper, Delay Defect Diagnosis Based Upon Statistical Timing Models – The First Step, by Krstic et al., addresses delay testing in deep sub-micron technology, proposes new delay defect diagnosis concepts, and shows how they compare with traditional logic detect diagnosis. Different diagnosis algorithms are described and evaluated using statistical defect injection and delay fault simulation. Finally, in the twelfth paper, Low Cost Software Based Self Testing of RISC Processor Cores, by Kranitis et al., the authors tackle the cost (development and tools) of testing processor cores and present a software-based self-testing methodology that supports low-speed and low-cost external testers. The methodology is validated by designing and testing a RISC processor. The guest editors would like to thank the DATE Executive Committee for supporting the development of this special issue, and would also like to thank April Sparks, Linda Meller and Stuart Govan at the IEE for their assistance in producing this issue. We would also like to sincerely thank all the authors for submitting their papers and the reviewers for keeping up with the very tight schedule that allowed us to complete this special issue as planned in less than seven months. We hope you enjoy this selection of some of the best papers from DATE 03. NORBERT WEHN University of Kaiserslautern, Germany Microelectronic System Design Research Group BASHIR M AL-HASHIMI University of Southampton, UK Electronic System Design Grou