2 research outputs found
Hardware Acceleration of the Embedded Zerotree Wavelet Algorithm
The goal of this project was to gain experience in designing and implementing a microelectronic system to acclerate the execution of a time-consuming software algorithm, the Embedded Zerotree Wavelet (EZW), which is used in multimedia applications. The algorithm was implemented using MATLAB to be certain it was fully understood and to serve as a validation reference. Then, the algorithm was mapped into a hardware description language, VHDL, and its resulting implementation verified with the golden reference. The hardware description was then targeted to a field-programmable gate array (FPGA). Significant acceleration was achieved since the hardware implementation in a FPGA (Xilinx Virtex-1000E using a 8.315 MHz clock) ran 10,000 times faster than the MATLAB implementation on a SUN-220 workstation. Additional speedup exploiting the parallel capabilities of the FPGA was not achieved since the EZW algorithm utilizes only sequential operations
ELECTRICAL CHARACTERIZATION, PHYSICS, MODELING AND RELIABILITY OF INNOVATIVE NON-VOLATILE MEMORIES
Enclosed in this thesis work it can be found the results of a three years long research
activity performed during the XXIV-th cycle of the Ph.D. school in Engineering Science of
the Università degli Studi di Ferrara. The topic of this work is concerned about the
electrical characterization, physics, modeling and reliability of innovative non-volatile
memories, addressing most of the proposed alternative to the floating-gate based
memories which currently are facing a technology dead end. Throughout the chapters of
this thesis it will be provided a detailed characterization of the envisioned replacements for
the common NOR and NAND Flash technologies into the near future embedded and
MPSoCs (Multi Processing System on Chip) systems. In Chapter 1 it will be introduced the
non-volatile memory technology with direct reference on nowadays Flash mainstream,
providing indications and comments on why the system designers should be forced to
change the approach to new memory concepts. In Chapter 2 it will be presented one of the
most studied post-floating gate memory technology for MPSoCs: the Phase Change
Memory. The results of an extensive electrical characterization performed on these
devices led to important discoveries such as the kinematics of the erase operation and
potential reliability threats in memory operations. A modeling framework has been
developed to support the experimental results and to validate them on projected scaled
technology. In Chapter 3 an embedded memory for automotive environment will be shown:
the SimpleEE p-channel memory. The characterization of this memory proven the
technology robustness providing at the same time new insights on the erratic bits
phenomenon largely studied on NOR and NAND counterparts. Chapter 4 will show the
research studies performed on a memory device based on the Nano-MEMS concept. This
particular memory generation proves to be integrated in very harsh environment such as
military applications, geothermal and space avionics. A detailed study on the physical
principles underlying this memory will be presented. In Chapter 5 a successor of the
standard NAND Flash will be analyzed: the Charge Trapping NAND. This kind of memory
shares the same principles of the traditional floating gate technology except for the storage
medium which now has been substituted by a discrete nature storage (i.e. silicon nitride
traps). The conclusions and the results summary for each memory technology will be
provided in Chapter 6. Finally, on Appendix A it will be shown the results of a recently
started research activity on the high level reliability memory management exploiting the
results of the studies for Phase Change Memories