Scalable VLSI Architecture for GF(p) Montgomery Modular Inverse Computation

Modular inverse computation is needed in several public key cryptographic applications. In this work, we present two VLSI hardware implementations used in the calculation of Montgomery modular inverse operation. The implementations are based on the same inversion algorithm, however, one is fixed (fully parallel) and the other is scalable. The scalable design is the novel modification performed on the fixed hardware to make it occupy a small area and operate within better or similar speed. Both hardware designs are compared based on their speed and area. The area of the scalable design is on average 42% smaller than the fixed one. The delay of the designs, however, depends on the actual data size and the maximum numbers the hardware can handle. As the actual data size approach the hardware limit the scalable hardware speedup reduces in comparison to the fixed one, but still its delay is practical

Scalable VLSI Architecture for GF(p) Montgomery Modular Inverse Computation

Modular inverse computation is needed in several public key cryptographic applications. In this work, we present two VLSI hardware implementations used in the calculation of Montgomery modular inverse operation. The implementations are based on the same inversion algorithm, however, one is fixed (fully parallel) and the other is scalable. The scalable design is the novel modification performed on the fixed hardware to make it occupy a small area and operate within better or similar speed. Both hardware designs are compared based on their speed and area. The area of the scalable design is on average 42% smaller than the fixed one. The delay of the designs, however, depends on the actual data size and the maximum numbers the hardware can handle. As the actual data size approach the hardware limit the scalable hardware speedup reduces in comparison to the fixed one, but still its delay is practical

High Speed Hardware Architecture to Compute GF(p) Montgomery Inversion with Scalability Features

Modular inversion is a fundamental process in several cryptographic systems. It can be computed in software or hardware, but hardware computation has been proven to be faster and more secure. This research focused on improving an old scalable inversion hardware architecture proposed in 2004 for finite field GF(p). The architecture comprises two parts, a computing unit and a memory unit. The memory unit holds all the data bits of computation whereas the computing unit performs all the arithmetic operations in word (digit) by word bases such that the design is scalable. The main objective of this paper is to show the cost and benefit of modifying the memory unit to include shifting, which was previously one of the tasks of the scalable computing unit. The study included remodeling the entire hardware architecture removing the shifter from the scalable computing part and embedding it in the non-scalable memory unit instead. This modification resulted in a speedup to the complete inversion process with an area increase due to the new memory shifting unit. Several design schemes have been compared giving the user the complete picture to choose from depending on the application need

Speeding up a scalable modular inversion hardware architecture

The modular inversion is a fundamental process in several cryptographic systems. It can be computed in software or hardware, but hardware computation proven to be faster and more secure. This research focused on improving an old scalable inversion hardware architecture proposed in 2004 for finite field GF(p). The architecture has been made of two parts, a computing unit and a memory unit. The memory unit is to hold all the data bits of computation whereas the computing unit performs all the arithmetic operations in word (digit) by word bases known as scalable method. The main objective of this project was to investigate the cost and benefit of modifying the memory unit to include parallel shifting, which was one of the tasks of the scalable computing unit. The study included remodeling the entire hardware architecture removing the shifter from the scalable computing part embedding it in the memory unit instead. This modification resulted in a speedup to the complete inversion process with an area increase due to the new memory shifting unit. Quantitative measurements of the speed area trade-off have been investigated. The results showed that the extra hardware to be added for this modification compared to the speedup gained, giving the user the complete picture to choose from depending on the application need.the British council in Saudi Arabia, KFUPM, Dr. Tatiana Kalganova at the Electrical & Computer Engineering Department of Brunel University in Uxbridg

GF(2k) Elliptic Curve Cryptographic Processor Architecture Based on Bit Level Pipelined Digit Serial Multiplication

New processor architecture for elliptic curve encryption is proposed in this paper. The architecture exploits projective coordinates to convert GF(2k) division needed in elliptic point operations into several multiplication steps. The processor has three GF(2k) multipliers implemented using bit-level pipelined digit serial computation. It is shown that this results in a faster operation than using fully parallel multipliers with the added advantage of requiring less area. The proposed architecture is a serious contender for implementing data security systems based on elliptic curve cryptography

GF(2k) Elliptic Curve Cryptographic Processor Architecture Based on Bit Level Pipelined Digit Serial Multiplication

New processor architecture for elliptic curve encryption is proposed in this paper. The architecture exploits projective coordinates to convert GF(2k) division needed in elliptic point operations into several multiplication steps. The processor has three GF(2k) multipliers implemented using bit-level pipelined digit serial computation. It is shown that this results in a faster operation than using fully parallel multipliers with the added advantage of requiring less area. The proposed architecture is a serious contender for implementing data security systems based on elliptic curve cryptography

Fast Elliptic Curve Cryptographic Processor Architecture Based On Three Parallel GF(2k) Bit Level Pipelined Digit Serial Multipliers

Unusual processor architecture for elliptic curve encryption is proposed in this paper. The architecture exploits projective coordinates (x=X/Z, y=Y/Z) to convert GF(2k) division needed in elliptic point operations into several multiplication steps. The processor has three GF(2k) multipliers implemented using bit-level pipelined digit serial computation. It is shown that this results in a faster operation than using fully parallel multipliers with the added advantage of requiring less area. The proposed architecture is a serious contender for implementing data security systems based on elliptic curve cryptography

VLSI Core Architecture For GF(P) Elliptic Curve Crypto Processor

A novel GF(p) crypto processor core architecture is presented in this paper. The core is used to implement GF(p) Elliptic Curve Cryptosystem (ECC). The architecture is such that a single core can be used to implement ECC or alternatively a two core solution can be adopted. As a result, the core architecture allows the exploitation of the parallelism that exists in elliptic curve point addition and doubling. The core architecture results in several advantages over conventional implementations with regard to speed and power consumption

VLSI Core Architecture For GF(P) Elliptic Curve Crypto Processor

A novel GF(p) crypto processor core architecture is presented in this paper. The core is used to implement GF(p) Elliptic Curve Cryptosystem (ECC). The architecture is such that a single core can be used to implement ECC or alternatively a two core solution can be adopted. As a result, the core architecture allows the exploitation of the parallelism that exists in elliptic curve point addition and doubling. The core architecture results in several advantages over conventional implementations with regard to speed and power consumption

Parallelizing GF(P) Elliptic Curve Cryptography Computations for Security and Speed

The elliptic curve cryptography can be observed as two levels of computations, upper scalar multiplication level and lower point operations level. We combine the inherited parallelism in both levels to reduce the delay and improve security against the simple power attack. The best security and speed performance is achieved when parallelizing the computation to eight parallel multiplication operations. This strategy is worth considering since it shows very attractive performance conclusions