6T-SRAM 1Mb Design with Test Structures and Post Silicon Validation

abstract: Static random-access memories (SRAM) are integral part of design systems as caches and data memories that and occupy one-third of design space. The work presents an embedded low power SRAM on a triple well process that allows body-biasing control. In addition to the normal mode operation, the design is embedded with Physical Unclonable Function (PUF) [Suh07] and Sense Amplifier Test (SA Test) mode. With PUF mode structures, the fabrication and environmental mismatches in bit cells are used to generate unique identification bits. These bits are fixed and known as preferred state of an SRAM bit cell. The direct access test structure is a measurement unit for offset voltage analysis of sense amplifiers. These designs are manufactured using a foundry bulk CMOS 55 nm low-power (LP) process. The details about SRAM bit-cell and peripheral circuit design is discussed in detail, for certain cases the circuit simulation analysis is performed with random variations embedded in SPICE models. Further, post-silicon testing results are discussed for normal operation of SRAMs and the special test modes. The silicon and circuit simulation results for various tests are presented.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Design and Evaluation of a Sub-1-Volt Read Flash Memory in a Standard 130 Nanometer CMOS Process

Nonvolatile memory design is a discipline that employs digital and analog circuit design techniques and requires knowledge of semiconductor physics and quantum mechanics. Methods for programming and erasing memory are discussed here, and simulation models are provided for Impact Hot Electron Injection (IHEI), Fowler-Nordheim (FN) tunneling, and direct tunneling. Extensive testing of analog memory cells was used to derive a set of equations that describe the oating-gate characteristics. Measurements of charge retention also revealed several leakage mechanisms, and methods for mitigating leakage are presented. Fabrication of ash memory in a standard CMOS process presents significant design challenges. The absence of multiple polysilicon layers requires that additional devices be used to control the oating-gate voltage. Furthermore high-voltage devices are often required to isolate the selected memory cells during write and erase cycles. However, a single-poly design allows portability to another standard process provided that the oating-gate characteristics are known. A ash memory system is presented here that has been fabricated in a standard 130 nanometer CMOS process. The design utilizes capacitive feedback to maintain desired injection current during programming. It also includes a sense amplifier design which features auto-zeroing of inherent offsets. Comparisons to existing memory designs show that a significant improvement in areal density was achieved through the elimination of on-die high-voltage charge pumps and switches. Measurements were performed over a range of clock frequencies and supply voltages. Results show that this memory system is capable of a read access time of 3.5 microseconds with a 1 megahertz clock while consuming less than 25 microwatts from a 1 volt supply. Operation down to 650 millivolts was confirmed where power consumption was reduced to only 3.4 microwatts. The low power consumption and high density of this ash memory make it an excellent choice for on-die firmware storage in battery-powered embedded applications

A Reliable Low-area Low-power PUF-based Key Generator

This paper reports the implementation of a lowarea low-power 128-bit PUF-based key generation module which exploits a novel Two-Stage IDentification (TSID) cell showing a higher noise immunity then a standard SRAM cell. In addition, the pre-selection technique introduced in [1] is applied. This results in a stable PUF response in spite of process and environmental variations thus requiring a low cost error correction algorithm in order to generate a reliable key. The adopted PUF cell array includes 1056 cells and shows a power consumption per bit of 4:2 W at 100MHz with an area per bit of 2:4 m2. In order to evaluate reliability and unpredictability of the generated key, extensive tests have been performed both on the raw PUF data and on the final key. The raw PUF data after pre-selection show a worst case intra-chip Hamming distance below 0:7%. After a total of more than 5 109 key reconstructions, no single fail has been detected

A Low Power 32 Bit CMOS ROM Using A Novel ATD Circuit

A low power high speed 32 Bit ROM circuit implemented on 0.18µm CMOS process has been presented in this paper. The circuit is build using a parallel ROM core structure and runs on 1.8 V supply voltage. A novel Address Transition Decoder (ATD) circuit is proposed which energizes the ROM components such as Row Decoder, Column Decoder, ROM core etc, for short time intervals when there is a transition in input address bits. The power consumed in ROM with proposed ATD circuit is 0.78 mW, which corresponds to 82.27% reduction in power as compared to ROM without ATD circuit (4.46 mW). At the output almost full signal swing has been achieved without using any sense amplifier. The implemented ROM has a very low latency of 0.56 ns.DOI:http://dx.doi.org/10.11591/ijece.v3i4.316

A fully integrated SRAM-based CMOS arbitrary waveform generator for analog signal processing

This dissertation focuses on design and implementation of a fully-integrated SRAM-based arbitrary waveform generator for analog signal processing applications in a CMOS technology. The dissertation consists of two parts: Firstly, a fully-integrated arbitrary waveform generator for a multi-resolution spectrum sensing of a cognitive radio applications, and an analog matched-filter for a radar application and secondly, low-power techniques for an arbitrary waveform generator. The fully-integrated low-power AWG is implemented and measured in a 0.18-¥ìm CMOS technology. Theoretical analysis is performed, and the perspective implementation issues are mentioned comparing the measurement results. Moreover, the low-power techniques of SRAM are addressed for the analog signal processing: Self-deactivated data-transition bit scheme, diode-connected low-swing signaling scheme with a short-current reduction buffer, and charge-recycling with a push-pull level converter for power reduction of asynchronous design. Especially, the robust latch-type sense amplifier using an adaptive-latch resistance and fully-gated ground 10T-SRAM bitcell in a 45-nm SOI technology would be used as a technique to overcome the challenges in the upcoming deep-submicron technologies.Ph.D.Committee Chair: Kim, Jongman; Committee Member: Kang, Sung Ha; Committee Member: Lee, Chang-Ho; Committee Member: Mukhopadhyay, Saibal; Committee Member: Tentzeris, Emmanouil