Prediction and mitigation of scour and scour damage to Vermont bridges

Over 300 Vermont bridges were damaged in the 2011 Tropical Storm Irene and many experienced significant scour. Successfully mitigating bridge scour in future flooding events depends on our ability to reliably estimate scour potential, design safe and economical foundation elements accounting for scour potential, design effective scour prevention and countermeasures, and design reliable and economically feasible monitoring systems, which served as the motivation for this study. This project sought to leverage data on existing Vermont bridges and case studies of bridge scour damage, and integrate available information from stream geomorphology to aid in prediction of bridge scour vulnerability. Tropical Storm Irene’s impact on Vermont bridges was used as a case study, providing damage information on a wide range of bridges throughout the State. Multiple data sources were combined in an effort to include data, which represents the complex, interconnected processes of stream stability and bridge scour, then identify and incorporate feature that would be useful in a probabilistic model to predict bridge susceptibility to scour damage. The research also sought to identify features that could be included in inspections and into a scour rating system that are capable of assessing network-level scour vulnerability of bridges more holistically. This research also sought to review existing scour countermeasures and scour monitoring technologies available in the literature and examine efficacy of new, indirect scour countermeasures and passive scour monitoring techniques. The specific objectives of this research were to: (1) review the literature and identify methods/technologies that are adaptable to Vermont; (2) analyze Tropical Storm Irene bridge damage information and observations by collecting and geo-referencing all available bridge records and stream geomorphic assessment data into a comprehensive database for identifying features that best represent bridge scour damage; (3) conduct watershed analysis on all bridges, including creation of stream power data to assess if watershed stream power improves the prediction of bridge scour damage; and (4) investigate new scour countermeasures and monitoring technologies, and provide recommendations on implementations

Fast and Robust Design of CMOS VCO for Optimal Performance

The exponentially growing design complexity with technological advancement calls for a large scope in the analog and mixed signal integrated circuit design automation. In the automation process, performance optimization under different environmental constraints is of prime importance. The analog integrated circuits design strongly requires addressing multiple competing performance objectives for optimization with ability to find global solutions in a constrained environment. The integrated circuit (IC) performances are significantly affected by the device, interconnect and package parasitics. Inclusion of circuit parasitics in the design phase along with performance optimization has become a bare necessity for faster prototyping. Besides this, the fabrication process variations have a predominant effect on the circuit performance, which is directly linked to the acceptability of manufactured integrated circuit chips. This necessitates a manufacturing process tolerant design. The development of analog IC design methods exploiting the computational intelligence of evolutionary techniques for optimization, integrating the circuit parasitic in the design optimization process in a more meaningful way and developing process fluctuation tolerant optimal design is the central theme of this thesis. Evolutionary computing multi-objective optimization techniques such as Non-dominated Sorting Genetic Algorithm-II and Infeasibility Driven Evolutionary Algorithm are used in this thesis for the development of parasitic aware design techniques for analog ICs. The realistic physical and process constraints are integrated in the proposed design technique. A fast design methodology based on one of the efficient optimization technique is developed and an extensive worst case process variation analysis is performed. This work also presents a novel process corner variation aware analog IC design methodology, which would effectively increase the yield of chips in the acceptable performance window. The performance of all the presented techniques is demonstrated through the application to CMOS ring oscillators, current starved and xi differential voltage controlled oscillators, designed in Cadence Virtuoso Analog Design Environment