On the Power of Fault Sensitivity Analysis and Collision Side-Channel Attacks in a Combined Setting

Abstract. At CHES 2010 two powerful new attacks were presented, namely the Fault Sensitivity Analysis and the Correlation Collision At-tack. This paper shows how these ideas can be combined to create even stronger attacks. Two solutions are presented; both extract leakage infor-mation by the fault sensitivity analysis method while each one applies a slightly different collision attack to deduce the secret information without the need of any hypothetical leakage model. Having a similar fault injec-tion method, one attack utilizes the non-uniform distribution of faulty ciphertext bytes while the other one exploits the data-dependent timing characteristics of the target combination circuit. The results when at-tacking several AES ASIC cores of the SASEBO LSI chips in different process technologies are presented. Successfully breaking the cores pro-tected against DPA attacks using either gate-level countermeasures or logic styles indicates the strength of the attacks.

Análisis de técnicas de routing diferencial en CriptoASICs: Adecuación del proceso previo de Place & Route

Universidad de Sevilla. Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométrico