Design of Energy-efficient Hierarchical Scheduling for Integrated Modular Avionics Systems

AbstractRecently the integrated modular avionics (IMA) architecture which introduces the concept of resource partitions becomes popular as an alternative to the traditional federated architecture. This study investigates the problem of designing hierarchical scheduling for IMA systems. The proposed scheduler model enables strong temporal partitioning, so that multiple hard real-time applications can be easily integrated into an uniprocessor platform. This paper derives the mathematic relationships among partition cycle, partition capacity and schedulability under the real-time condition, and then proposes an algorithm for optimizing partition parameters. Real-time tasks with arbitrary deadlines are considered for generality. To further improve the basic algorithm and reduce the energy consumption for embedded systems in aircraft, a power optimization approach is also proposed by exploiting the slack time. Experimental results show that the designed system can guarantee the hard real-time requirement and reduce the power consumption by at least 14%

On the tailoring of CAST-32A certification guidance to real COTS multicore architectures

The use of Commercial Off-The-Shelf (COTS) multicores in real-time industry is on the rise due to multicores' potential performance increase and energy reduction. Yet, the unpredictable impact on timing of contention in shared hardware resources challenges certification. Furthermore, most safety certification standards target single-core architectures and do not provide explicit guidance for multicore processors. Recently, however, CAST-32A has been presented providing guidance for software planning, development and verification in multicores. In this paper, from a theoretical level, we provide a detailed review of CAST-32A objectives and the difficulty of reaching them under current COTS multicore design trends; at experimental level, we assess the difficulties of the application of CAST-32A to a real multicore processor, the NXP P4080.This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015-65316-P and the HiPEAC Network of Excellence. Jaume Abella has been partially supported by the MINECO under Ramon y Cajal grant RYC-2013-14717.Peer ReviewedPostprint (author's final draft

VSO: Self-organizing Spatial Publish Subscribe

Abstract-Spatial publish subscribe (SPS) is a basic primitive underlying many real-time, interactive applications such as online games or discrete-time simulations. Supporting SPS on a large-scale, however, requires sufficient resources and proper load distribution among the simulation units. For load distribution, existing mechanisms either use a static partitioning, such that over-provisioning or overloading are bound to occur, or require manual adjustments unsuitable for massive workloads. We describe Voronoi Self-organizing Overlay (VSO) [1], which extends a Voronoi-based Overlay network (VON) to automatically partition and manage a logical space to support SPS. Efficient resource usage thus is possible as only the units necessary to maintain the system are used. Load is also balanced among the resource units so that overloading or overprovisioning can be avoided. We use simulations to verify our design and describe some preliminary results

DeepPicar: A Low-cost Deep Neural Network-based Autonomous Car

We present DeepPicar, a low-cost deep neural network based autonomous car platform. DeepPicar is a small scale replication of a real self-driving car called DAVE-2 by NVIDIA. DAVE-2 uses a deep convolutional neural network (CNN), which takes images from a front-facing camera as input and produces car steering angles as output. DeepPicar uses the same network architecture---9 layers, 27 million connections and 250K parameters---and can drive itself in real-time using a web camera and a Raspberry Pi 3 quad-core platform. Using DeepPicar, we analyze the Pi 3's computing capabilities to support end-to-end deep learning based real-time control of autonomous vehicles. We also systematically compare other contemporary embedded computing platforms using the DeepPicar's CNN-based real-time control workload. We find that all tested platforms, including the Pi 3, are capable of supporting the CNN-based real-time control, from 20 Hz up to 100 Hz, depending on hardware platform. However, we find that shared resource contention remains an important issue that must be considered in applying CNN models on shared memory based embedded computing platforms; we observe up to 11.6X execution time increase in the CNN based control loop due to shared resource contention. To protect the CNN workload, we also evaluate state-of-the-art cache partitioning and memory bandwidth throttling techniques on the Pi 3. We find that cache partitioning is ineffective, while memory bandwidth throttling is an effective solution.Comment: To be published as a conference paper at RTCSA 201