Trade-offs between gate oxide protection and performance in SiC MOSFETs

The reliability of gate oxides in SiC MOSFETs has come under increased scrutiny due to reduced performance under time dependent dielectric breakdown and increased threshold voltage instability. This paper investigates how 10% gate voltage (V GS ) derating in SiC MOSFETs can be implemented with minimal impact on loss performance. Using experimental measurements and electrothermal simulations of power converters, the trade-off between reduced V GS and conversion loss is investigated. It is shown that 10% V GS de-rating increases the ON-state resistance by 10% and the turn-ON switching energy by 7% average while the turn-OFF switching energy is unaffected. The low temperature sensitivity of the ON-state losses in SiC MOSFETs can be exploited since the rise in junction temperature due to V GS derating is marginal, unlike Si devices where ON-state resistance rises significantly with temperature. The load current and switching frequency influences the effectiveness of V GS derating. It is also shown that reducing the gate drive output impedance can compensate for V GS derating at high switching frequencies, with reduced total loss penalization. This may be important for protecting the gate oxide and enhancing its reliability

Accelerated tests on Si and SiC power transistors with thermal, fastand ultra-fast neutrons

Neutron test campaigns on silicon (Si) and silicon carbide (SiC) power MOSFETs and IGBTs were conducted at the TRIGA (Training, Research, Isotopes, General Atomics) Mark II (Pavia, Italy) nuclear reactor and ChipIr-ISIS Neutron and Muon Source (Didcot, U.K.) facility. About 2000 power transistors made by STMicroelectronics were tested in all the experiments. Tests with thermal and fast neutrons (up to about 10 MeV) at the TRIGA Mark II reactor showed that single-event burnout (SEB) failures only occurred at voltages close to the rated drain-source voltage. Thermal neutrons did not induce SEB, nor degradation in the electrical parameters of the devices. SEB failures during testing at ChipIr with ultra-fast neutrons (1-800 MeV) were evaluated in terms of failure in time (FIT) versus derating voltage curves according to the JEP151 procedure of the Joint Electron Device Engineering Council (JEDEC). These curves, even if scaled with die size and avalanche voltage, were strongly linked to the technological processes of the devices, although a common trend was observed that highlighted commonalities among the failures of different types of MOSFETs. In both experiments, we observed only SEB failures without single-event gate rupture (SEGR) during the tests. None of the power devices that survived the neutron tests were degraded in their electrical performances. A study of the worst-case bias condition (gate and/or drain) during irradiation was performed

Accelerated Tests on Si and SiC Power Transistors with Thermal, Fast and Ultra-Fast Neutrons

Neutron test campaigns on silicon (Si) and silicon carbide (SiC) power MOSFETs and IGBTs were conducted at the TRIGA (Training, Research, Isotopes, General Atomics) Mark II (Pavia, Italy) nuclear reactor and ChipIr-ISIS Neutron and Muon Source (Didcot, U.K.) facility. About 2000 power transistors made by STMicroelectronics were tested in all the experiments. Tests with thermal and fast neutrons (up to about 10 MeV) at the TRIGA Mark II reactor showed that single-event burnout (SEB) failures only occurred at voltages close to the rated drain-source voltage. Thermal neutrons did not induce SEB, nor degradation in the electrical parameters of the devices. SEB failures during testing at ChipIr with ultra-fast neutrons (1-800 MeV) were evaluated in terms of failure in time (FIT) versus derating voltage curves according to the JEP151 procedure of the Joint Electron Device Engineering Council (JEDEC). These curves, even if scaled with die size and avalanche voltage, were strongly linked to the technological processes of the devices, although a common trend was observed that highlighted commonalities among the failures of different types of MOSFETs. In both experiments, we observed only SEB failures without single-event gate rupture (SEGR) during the tests. None of the power devices that survived the neutron tests were degraded in their electrical performances. A study of the worst-case bias condition (gate and/or drain) during irradiation was performed