2,114 research outputs found

    Model-based Reliability Analysis of Power Electronic Systems

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    Design for reliability and robustness tool platform for power electronic systems:Study case on motor drive applications

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    Fault Diagnosis and Condition Monitoring of Power Electronic Components Using Spread Spectrum Time Domain Reflectometry (SSTDR) and the Concept of Dynamic Safe Operating Area (SOA)

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    Title from PDF of title page viewed April 1, 2021Dissertation advisors: Faisal Khan and Yong ZengVitaIncludes bibliographical references ( page 117-132)Thesis (Ph.D.)--School of Computing and Engineering and Department of Mathematics and Statistics. University of Missouri--Kansas City, 2021Fault diagnosis and condition monitoring (CM) of power electronic components with a goal of improving system reliability and availability have been one of the major focus areas in the power electronics field in the last decades. Power semiconductor devices such as metal oxide semiconductor field-effect transistor (MOSFET) and insulated-gate bipolar transistor (IGBT) are considered to be the most fragile element of the power electronic systems and their reliability degrades with time due to mechanical and thermo-electrical stresses, which ultimately leads to a complete failure of the overall power conversion systems. Therefore, it is important to know the present state of health (SOH) of the power devices and the remaining useful life (RUL) of a power converter in order to perform preventive scheduled maintenance, which will eventually lead to increased system availability and reduced cost. In conventional practice, device aging and lifetime prediction techniques rely on the estimation of the meantime to failure (MTTF), a value that represents the expected lifespan of a device. MTTF predicts expected lifespan, but cannot adequately predict failures attributed to unusual circumstances or continuous overstress and premature degradation. This inability is due in large part to the fact that it considers the device safe operating area (SOA) or voltage and current ride-through capability to be independent of SOH. However, we experimentally proved that SOA of any semiconductor device goes down with the increased level of aging, and therefore, the probability of occurrence of over-voltage/current situation increases. As a result, the MTTF of the device as well as the overall converter reliability reduces with aging. That said, device degradation can be estimated by accomplishing an accurate online degradation monitoring tool that will determine the dynamic SOA. The correlation between aging and dynamic SOA gives us the useful remaining life of the device or the availability of a circuit. For this monitoring tool, spread spectrum time domain reflectometry (SSTDR) has been proposed and was successfully implemented in live power converters. In SSTDR, a high-frequency sine-modulated pseudo-noise sequence (SMPNS) is sent through the system, and reflections from age-related impedance discontinuities return to the test end where they are analyzed. In the past, SSTDR has been successfully used for device degradation detection in power converters while running at static conditions. However, the rapid variation in impedance throughout the entire live converter circuit caused by the fast-switching operation makes CM more challenging while using SSTDR. The algorithms and techniques developed in this project have overcome this challenge and demonstrated that the SSTDR test data are consistent with the aging of the power devices and do not affect the switching performance of the modulation process even the test signal is applied across the gate-source interface of the power MOSFET. This implies that the SSTDR technique can be integrated with the gate driver module, thereby creating a new platform for an intelligent gate-driver architecture (IGDA) that enables real-time health monitoring of power devices while performing features offered by a commercially available driver. Another application of SSTDR in power electronic systems is the ground fault prediction and detection technique for PV arrays. Protecting PV arrays from ground faults that lead to fire hazards and power loss is imperative to maintaining safe and effective solar power operations. Unlike many standard detection methods, SSTDR does not depend on fault current, therefore, can be implemented for testing ground faults at night or low illumination. However, wide variation in impedance throughout different materials and interconnections makes fault location more challenging than fault detection. This barrier was surmounted by the SSTDR-based fault detection algorithm developed in this project. The proposed algorithm was accounted for any variation in the number of strings, fault resistance, and the number of faults. In addition to its general utility for fault detection, the proposed algorithm can identify the location of multiple faults using only a single measurement point, thereby working as a preventative measure to protect the entire system at a reduced cost. Within the scope of the research work on SSTDR-based fault diagnosis and CM of power electronic components, a cell-level SOH measurement tool has been proposed that utilizes SSTDR to detect the location and aging of individual degraded cells in a large series-parallel connected Li-ion battery pack. This information of cell level SOH along with the respective cell location is critical to calculating the SOH of a battery pack and its remaining useful lifetime since the initial SOH of Li-ion cells varies under different manufacturing processes and operating conditions, causing them to perform inconsistently and thereby affect the performance of the entire battery pack in real-life applications. Unfortunately, today’s BMS considers the SOH of the entire battery pack/cell string as a single SOH and therefore, cannot monitor the SOH at the cell level. A healthy battery string has a specific impedance between the two terminals, and any aged cell in that string will change the impedance value. Since SSTDR can characterize the impedance change in its propagation path along with its location, it can successfully locate the degraded cell in a large battery pack and thereby, can prevent premature failure and catastrophic danger by performing scheduled maintenance.Introduction -- Background study and literature review -- Fundamentals of Spread Spectrum Time Domain Reflectometry (SSTDR): A new method for testing electronics live -- Accelerated aging test bench: design and implementation -- Condition monitoring of power switching in live power switching devices in live power electronic converters using SSTDR -- An irradiance-independent, robust ground-fault detection scheme for PV arrays based on SSTDR -- Detection of degraded/aged cell in a LI-Ion battery pack using SSTDR -- Dynamiv safe operating area (SOA) of power semiconductor devices -- Conclusion and future researc

    Advanced Modeling of SiC Power MOSFETs aimed to the Reliability Evaluation of Power Modules

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    Hourly Dispatching Wind-Solar Hybrid Power System with Battery-Supercapacitor Hybrid Energy Storage

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    This dissertation demonstrates a dispatching scheme of wind-solar hybrid power system (WSHPS) for a specific dispatching horizon for an entire day utilizing a hybrid energy storage system (HESS) configured by batteries and supercapacitors. Here, wind speed and solar irradiance are predicted one hour ahead of time using a multilayer perceptron Artificial Neural Network (ANN), which exhibits satisfactory performance with good convergence mapping between input and target output data. Furthermore, multiple state of charge (SOC) controllers as a function of energy storage system (ESS) SOC are developed to accurately estimate the grid reference power (PGrid,ref) for each dispatching period. A low pass filter (LPF) is employed to decouple the power between a battery and a supercapacitor (SC), and the cost optimization of the HESS is computed based on the time constant of the LPF through extensive simulations. Besides, the optimum value of depth of discharge for ESS considering both cycling and calendar expenses has been investigated to optimize the life cycle cost of the ESS, which is vital for minimizing the cost of a dispatchable wind-solar power scheme. Finally, the proposed ESS control algorithm is verified by conducting control hardware-in-the loop (CHIL) experiments in a real-time digital simulator (RTDS) platform

    Power Semiconductors for An Energy-Wise Society

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    This IEC White Paper establishes the critical role that power semiconductors play in transitioning to an energy wise society. It takes an in-depth look at expected trends and opportunities, as well as the challenges surrounding the power semiconductors industry. Among the significant challenges mentioned is the need for change in industry practices when transitioning from linear to circular economies and the shortage of skilled personnel required for power semiconductor development. The white paper also stresses the need for strategic actions at the policy-making level to address these concerns and calls for stronger government commitment, policies and funding to advance power semiconductor technologies and integration. It further highlights the pivotal role of standards in removing technical risks, increasing product quality and enabling faster market acceptance. Besides noting benefits of existing standards in accelerating market growth, the paper also identifies the current standardization gaps. The white paper emphasizes the importance of ensuring a robust supply chain for power semiconductors to prevent supply-chain disruptions like those seen during the COVID-19 pandemic, which can have widespread economic impacts.The white paper highlights the importance of inspiring young professionals to take an interest in power semiconductors and power electronics, highlighting the potential to make a positive impact on the world through these technologies.The white paper concludes with recommendations for policymakers, regulators, industry and other IEC stakeholders for collaborative structures and accelerating the development and adoption of standards

    Development of a multilevel converter topology for transformer-less connection of renewable energy systems

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    The global need to reduce dependence on fossil fuels for electricity production has become an ongoing research theme in the last decade. Clean energy sources (such as wind energy and solar energy) have considerable potential to reduce reliance on fossil fuels and mitigate climate change. However, wind energy is going to become more mainstream due to technological advancement and geographical availability. Therefore, various technologies exist to maximize the inherent advantages of using wind energy conversion systems (WECSs) to generate electrical power. One important technology is the power electronics interface that enables the transfer and effective control of electrical power from the renewable energy source to the grid through the filter and isolation transformer. However, the transformer is bulky, generates losses, and is also very costly. Therefore, the term "transformer-less connection" refers to eliminating a step-up transformer from the WECS, while the power conversion stage performs the conventional functions of a transformer. Existing power converter configurations for transformer-less connection of a WECS are either based on the generator-converter configuration or three-stage power converter configuration. These configurations consist of conventional multilevel converter topologies and two-stage power conversion between the generator-side converter topology and the high-order filter connected to the collection point of the wind power plant (WPP). Thus, the complexity and cost of these existing configurations are significant at higher voltage and power ratings. Therefore, a single-stage multilevel converter topology is proposed to simplify the power conversion stage of a transformer-less WECS. Furthermore, the primary design challenges – such as multiple clamping devices, multiple dc-link capacitors, and series-connected power semiconductor devices – have been mitigated by the proposed converter topology. The proposed converter topology, known as the "tapped inductor quasi-Z-source nested neutral-point-clamped (NNPC) converter," has been analyzed, and designed, and a prototype of the topology developed for experimental verification. A field-programmable gate array (FPGA)-based modulation technique and voltage balancing control technique for maintaining the clamping capacitor voltages was developed. Hence, the proposed converter topology presents a single-stage power conversion configuration. Efficiency analysis of the proposed converter topology has been studied and compared to the intermediate and grid-side converter topology of a three-stage power converter configuration. A direct current (DC) component minimization technique to minimize the dc component generated by the proposed converter topology was investigated, developed, and verified experimentally. The proposed dc component minimization technique consists of a sensing and measurement circuitry with a digital notch filter. This thesis presents a detailed and comprehensive overview of the existing power converter configurations developed for transformer-less WECS applications. Based on the developed 2 comparative benchmark factor (CBF), the merits and demerits of each power converter configuration in terms of the component counts and grid compliance have been presented. In terms of cost comparison, the three-stage power converter configuration is more cost-effective than the generatorconverter configuration. Furthermore, the cost-benefit analysis of deploying a transformer-less WECSs in a WPP is evaluated and compared with conventional WECS in a WPP based on power converter configurations and collection system. Overall, the total cost of the collection system of WPP with transformer-less WECSs is about 23% less than the total cost of WPP with conventional WECs. The derivation and theoretical analysis of the proposed five-level tapped inductor quasi-Z-source NNPC converter topology have been presented, emphasizing its operating principles, steady-state analysis, and deriving equations to calculate its inductance and capacitance values. Furthermore, the FPGA implementation of the proposed converter topology was verified experimentally with a developed prototype of the topology. The efficiency of the proposed converter topology has been evaluated by varying the switching frequency and loads. Furthermore, the proposed converter topology is more efficient than the five-level DC-DC converter with a five-level diode-clamped converter (DCC) topology under the three-stage power converter configuration. Also, the cost analysis of the proposed converter topology and the conventional converter topology shows that it is more economical to deploy the proposed converter topology at the grid side of a transformer-less WECS
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