1 research outputs found
Practical Guidelines for Approaching the Implementation of Neural Networks on FPGA for PAPR Reduction in Vehicular Networks
Nowadays, the sensor community has become wireless, increasing their potential and applications. In particular, these emerging technologies are promising for vehicles' communications (V2V) to dramatically reduce the number of fatal roadway accidents by providing early warnings.
The ECMA-368 wireless communication standard has been developed and used in wireless sensor
networks and it is also proposed to be used in vehicular networks. It adopts Multiband Orthogonal
Frequency Division Multiplexing (MB-OFDM) technology to transmit data. However, the large
power envelope fluctuation of OFDM signals limits the power efficiency of the High Power Amplifier
(HPA) due to nonlinear distortion. This is especially important for mobile broadband wireless and
sensors in vehicular networks. Many algorithms have been proposed for solving this drawback.
However, complexity and implementations are usually an issue in real developments. In this paper,
the implementation of a novel architecture based on multilayer perceptron artificial neural networks
on a Field Programmable Gate Array (FPGA) chip is evaluated and some guidelines are drawn
suitable for vehicular communications. The proposed implementation improves performance in
terms of Peak to Average Power Ratio (PAPR) reduction, distortion and Bit Error Rate (BER) with
much lower complexity. Two different chips have been used, namely, Xilinx and Altera and a
comparison is also provided. As a conclusion, the proposed implementation allows a minimal
consumption of the resources jointly with a higher maximum frequency, higher performance and
lower complexity.This work has been partly funded by projects TERESA-ADA (TEC2017-90093-C3-2-R)
(MINECO/AEI/FEDER, UE) and ELISA (TEC2014-59255-C3-3-R)