5,160 research outputs found

    Iterative joint channel and data estimation for rank-deficient MIMO-OFDM

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    In this paper we propose a turbo-detected multi-antenna-multi-carrier receiver scheme. Following the philosophy of the turbo processing, our turbo MIMO-OFDM receiver comprises a succession of detection modules, namely the channel estimator, the space-time detector and the decoder, which iteratively exchange soft bit-related information and thus facilitate a substantial improvement of the overall system performance. In this paper we analyze the achievable performance of the iterative system proposed with the aim of documenting the various design trade-offs, such as the achievable error-rate performance, the attainable data-rate as well as the associated computational complexity. Specifically, we report a virtually error-free performance for a rate-1/2 turbo-coded 8x8-QPSK-OFDM system, exhibiting an effective throughput of 8*2/2=8 bits/sec/Hz and having a pilot overhead of only 10%, at SNR of 7.5dB and normalized Doppler frequency of 0.003, which corresponds to a mobile terminal speed of about 65 km/h

    Near-Instantaneously Adaptive HSDPA-Style OFDM Versus MC-CDMA Transceivers for WIFI, WIMAX, and Next-Generation Cellular Systems

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    Burts-by-burst (BbB) adaptive high-speed downlink packet access (HSDPA) style multicarrier systems are reviewed, identifying their most critical design aspects. These systems exhibit numerous attractive features, rendering them eminently eligible for employment in next-generation wireless systems. It is argued that BbB-adaptive or symbol-by-symbol adaptive orthogonal frequency division multiplex (OFDM) modems counteract the near instantaneous channel quality variations and hence attain an increased throughput or robustness in comparison to their fixed-mode counterparts. Although they act quite differently, various diversity techniques, such as Rake receivers and space-time block coding (STBC) are also capable of mitigating the channel quality variations in their effort to reduce the bit error ratio (BER), provided that the individual antenna elements experience independent fading. By contrast, in the presence of correlated fading imposed by shadowing or time-variant multiuser interference, the benefits of space-time coding erode and it is unrealistic to expect that a fixed-mode space-time coded system remains capable of maintaining a near-constant BER

    A Two-Phase Maximum-Likelihood Sequence Estimation for Receivers with Partial CSI

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    The optimality of the conventional maximum likelihood sequence estimation (MLSE), also known as the Viterbi Algorithm (VA), relies on the assumption that the receiver has perfect knowledge of the channel coefficients or channel state information (CSI). However, in practical situations that fail the assumption, the MLSE method becomes suboptimal and then exhaustive checking is the only way to obtain the ML sequence. At this background, considering directly the ML criterion for partial CSI, we propose a two-phase low-complexity MLSE algorithm, in which the first phase performs the conventional MLSE algorithm in order to retain necessary information for the backward VA performed in the second phase. Simulations show that when the training sequence is moderately long in comparison with the entire data block such as 1/3 of the block, the proposed two-phase MLSE can approach the performance of the optimal exhaustive checking. In a normal case, where the training sequence consumes only 0.14 of the bandwidth, our proposed method still outperforms evidently the conventional MLSE.Comment: 5 pages and 4 figure

    Software Defined Radio Implementation of Carrier and Timing Synchronization for Distributed Arrays

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    The communication range of wireless networks can be greatly improved by using distributed beamforming from a set of independent radio nodes. One of the key challenges in establishing a beamformed communication link from separate radios is achieving carrier frequency and sample timing synchronization. This paper describes an implementation that addresses both carrier frequency and sample timing synchronization simultaneously using RF signaling between designated master and slave nodes. By using a pilot signal transmitted by the master node, each slave estimates and tracks the frequency and timing offset and digitally compensates for them. A real-time implementation of the proposed system was developed in GNU Radio and tested with Ettus USRP N210 software defined radios. The measurements show that the distributed array can reach a residual frequency error of 5 Hz and a residual timing offset of 1/16 the sample duration for 70 percent of the time. This performance enables distributed beamforming for range extension applications.Comment: Submitted to 2019 IEEE Aerospace Conferenc

    Complexity evaluation for the implementation of a pre-FFT equalizer in an OFDM receiver

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    A pre-FFT equalizer design for application to Hiperlan/2

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    Programmable digital modem

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    The design of the Programmable Digital Modem (PDM) is outlined. The PDM will be capable of operating with numerous modulation techniques including: 2-, 4-, 8- and 16-ary phase shift keying (PSK), minimum shift keying (MSK), and 16-ary quadrature amplitude modulation (QAM), with spectral occupancy from 1.2x to 2x the data symbol rate. It will also be programmable for transmission rates ranging from 2.34 to 300 Mbit/s, where the maximum symbol rate is 75 Msymbol/s. Furthermore, these parameters will be executable in independent burst, dependent burst, or continuous mode. In dependent burst mode the carrier and clock oscillator sources are common from burst to burst. To achieve as broad a set of requirements as these, it is clear that the essential signal processing must be digital. In addition, to avoid hardware changes when the operational parameters are changed, a fixed interface to an analog intermediate frequency (IF) is necessary for transmission; and, common system level architectures are necessary for the modulator and demodulator. Lastly, to minimize size and power, as much of the design as possible will be implemented with application specific integrated circuit (ASIC) chips
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