Noise and Blocker Cancellation Techniques for Power and Area Efficient Wireless Receivers

The design of mobile wireless devices has always focused on reducing power, area, and cost. This dissertation proposes two techniques that are leveraged to save power and area and therefore cost. The first techniques reduces the noise in the receiver and results in a relaxed power requirement. The second technique filters the blocker on-chip and allows for the removal of bulky off-chip components in a wireless system. In the first technique a two-path noise-cancellation architecture is used that reduces the noise in the receiver front end. A prototype ultra-wideband (UWB) receiver is designed and fabricated based on this idea in a 130 nm CMOS process. The fabricated prototype achieves an energy efficiency of 0.48 nJ/bit with a sensitivity of -82 dBm while operating across a wide data rate range of 0.1-25 Mb/s. The second technique is a blocker filtering scheme that extracts the clock from the blocker and helps eliminate bulky off-chip surface acoustic wave (SAW) filter components. Implemented in a 65 nm CMOS process, the filter is able to track the blocker within 1 to 1.6 GHz and provides better than 10 dB of rejection at the notch frequency for blockers from -40 dBm to -10 dBm