Design of application-specific instruction set processors with asynchronous methodology for embedded digital signal processing applications.

Kwok Yan-lun Andy.Thesis submitted in: November 2004.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.Includes bibliographical references (leaves 133-137).Abstracts in English and Chinese.Abstract --- p.i摘要 --- p.iiAcknowledgements --- p.iiiList of Figures --- p.viiList of Tables and Examples --- p.xChapter 1. --- Introduction --- p.1Chapter 1.1. --- Motivation --- p.1Chapter 1.2. --- Objective and Approach --- p.4Chapter 1.3. --- Thesis Organization --- p.5Chapter 2. --- Related Work --- p.7Chapter 2.1. --- Coverage --- p.7Chapter 2.2. --- ASIP Design Methodologies --- p.8Chapter 2.3. --- Asynchronous Technology on Processors --- p.12Chapter 2.4. --- Summary --- p.14Chapter 3. --- Asynchronous Design Methodology --- p.15Chapter 3.1. --- Overview --- p.15Chapter 3.2. --- Asynchronous Design Style --- p.17Chapter 3.2.1. --- Micropipelines --- p.17Chapter 3.2.2. --- Fine-grain Pipelining --- p.20Chapter 3.2.3. --- Globally-Asynchronous Locally-Synchronous (GALS) Design --- p.22Chapter 3.3. --- Advantages of GALS in ASIP Design --- p.27Chapter 3.3.1. --- Reuse of Synchronous and Asynchronous IP --- p.27Chapter 3.3.2. --- Fine Tuning of Performance and Power Consumption --- p.27Chapter 3.3.3. --- Synthesis-based Design Flow --- p.28Chapter 3.4. --- Design of GALS Asynchronous Wrapper --- p.28Chapter 3.4.1. --- Handshake Protocol --- p.28Chapter 3.4.2. --- Pausible Clock Generator --- p.29Chapter 3.4.3. --- Port Controllers --- p.30Chapter 3.4.4. --- Performance of the Asynchronous Wrapper --- p.33Chapter 3.5. --- Summary --- p.35Chapter 4. --- Platform Based ASIP Design Methodology --- p.36Chapter 4.1. --- Platform Based Approach --- p.36Chapter 4.1.1. --- The Definition of Our Platform --- p.37Chapter 4.1.2. --- The Definition of the Platform Based Design --- p.37Chapter 4.2. --- Platform Architecture --- p.38Chapter 4.2.1. --- The Nature of DSP Algorithms --- p.38Chapter 4.2.2. --- Design Space of Datapath Optimization --- p.46Chapter 4.2.3. --- Proposed Architecture --- p.49Chapter 4.2.4. --- The Strategy of Realizing an Optimized Datapath --- p.51Chapter 4.2.5. --- Pipeline Organization --- p.59Chapter 4.2.6. --- GALS Partitioning --- p.61Chapter 4.2.7. --- Operation Mechanism --- p.63Chapter 4.3. --- Overall Design Flow --- p.67Chapter 4.4. --- Summary --- p.70Chapter 5. --- Design of the ASIP Platform --- p.72Chapter 5.1. --- Design Goal --- p.72Chapter 5.2. --- Instruction Fetch --- p.74Chapter 5.2.1. --- Instruction fetch unit --- p.74Chapter 5.2.2. --- Zero-overhead loops and Subroutines --- p.75Chapter 5.3. --- Instruction Decode --- p.77Chapter 5.3.1. --- Instruction decoder --- p.77Chapter 5.3.2. --- The Encoding of Parallel and Complex Instructions --- p.80Chapter 5.4. --- Datapath --- p.81Chapter 5.4.1. --- Base Functional Units --- p.81Chapter 5.4.2. --- Functional Unit Wrapper Interface --- p.83Chapter 5.5. --- Register File Systems --- p.84Chapter 5.5.1. --- Memory Hierarchy --- p.84Chapter 5.5.2. --- Register File Organization --- p.85Chapter 5.5.3. --- Address Generation --- p.93Chapter 5.5.4. --- Load and Store --- p.98Chapter 5.6. --- Design Verification --- p.100Chapter 5.7. --- Summary --- p.104Chapter 6. --- Case Studies --- p.105Chapter 6.1. --- Objective --- p.105Chapter 6.2. --- Approach --- p.105Chapter 6.3. --- Based versus Optimized --- p.106Chapter 6.3.1. --- Matrix Manipulation --- p.106Chapter 6.3.2. --- Autocorrelation --- p.109Chapter 6.3.3. --- CORDIC --- p.110Chapter 6.4. --- Optimized versus Advanced Commercial DSPs --- p.113Chapter 6.4.1. --- Introduction to TMS320C62x and SC140 --- p.113Chapter 6.4.2. --- Results --- p.115Chapter 6.5. --- Summary --- p.116Chapter 7. --- Conclusion --- p.118Chapter 7.1. --- When ASIPs encounter asynchronous --- p.118Chapter 7.2. --- Contributions --- p.120Chapter 7.3. --- Future Directions --- p.121Chapter A --- Synthesis of Extended Burst-Mode Asynchronous Finite State Machine --- p.122Chapter B --- Base Instruction Set --- p.124Chapter C --- Special Registers --- p.127Chapter D --- Synthesizable Model of GALS Wrapper --- p.130Reference --- p.13

An ALU design using a novel asynchronous pipeline architecture.

Tang, Tin-Yau.Thesis (M.Phil.)--Chinese University of Hong Kong, 2000.Includes bibliographical references (leaves 122-123).Abstracts in English and Chinese.Table of Content --- p.2List of Figures --- p.4List of Tables --- p.6Acknowledgements --- p.7Abstract --- p.8Chapter I. --- Introduction --- p.11Chapter 1.1 --- Asynchronous Design --- p.12Chapter 1.1.1 --- What is asynchronous design? --- p.12Chapter 1.1.2 --- Potential advantages of asynchronous design --- p.12Chapter 1.1.3 --- Design methodology for asynchronous circuit --- p.15Chapter 1.1.4 --- Difficulty and limitation of asynchronous design --- p.19Chapter 1.2 --- Pipeline and Asynchronous Pipeline --- p.21Chapter 1.2.1 --- What is pipeline? --- p.21Chapter 1.2.2 --- Property of pipeline system --- p.21Chapter 1.2.3 --- Asynchronous pipeline --- p.23Chapter 1.3 --- Design Motivation --- p.26Chapter II. --- Design Theory --- p.27Chapter 2.1 --- A Novel Asynchronous Pipeline Architecture --- p.28Chapter 2.1.1 --- The problem of classical asynchronous pipeline --- p.28Chapter 2.1.2 --- The new handshake cell --- p.28Chapter 2.1.3 --- The modified asynchronous pipeline architecture --- p.29Chapter 2.2 --- Design of the ALU --- p.36Chapter 2.2.1 --- The functionality of ALU --- p.36Chapter 2.2.2 --- The choice of the adder and the BLC adder --- p.37Chapter III. --- Implementation --- p.41Chapter 3.1 --- ALU Detail --- p.42Chapter 3.1.1 --- Global arrangement --- p.42Chapter 3.1.2 --- Shift and Rotate --- p.46Chapter 3.1.3 --- Flags generation --- p.49Chapter 3.2 --- Application of the Pipeline Architecture --- p.53Chapter 3.2.1 --- The reset network for the pipeline architecture --- p.53Chapter 3.2.2 --- Handshake simplification for splitting and joining of datapath. --- p.55Chapter IV. --- Result --- p.59Chapter 4.1 --- Measurement and Simulation Result --- p.60Chapter 4.2 --- Global Routing Parasites --- p.63Chapter 4.3 --- Low Power Application --- p.65Chapter V. --- Conclusion --- p.67Chapter VI. --- Appendixes --- p.69Chapter 6.1 --- The Small Micro-coded Processor --- p.69Chapter 6.2 --- The Instruction Table of the ALU --- p.70Chapter 6.3 --- Measurement and Simulation Result --- p.71Chapter 6.4 --- "VHDLs, Schematics and Layout" --- p.87Chapter 6.5 --- Pinout of the Test Chip --- p.120Chapter 6.6 --- The Chip Photo --- p.121Chapter VII. --- Reference --- p.12