CRAID: Online RAID upgrades using dynamic hot data reorganization

Current algorithms used to upgrade RAID arrays typically require large amounts of data to be migrated, even those that move only the minimum amount of data required to keep a balanced data load. This paper presents CRAID, a self-optimizing RAID array that performs an online block reorganization of frequently used, long-term accessed data in order to reduce this migration even further. To achieve this objective, CRAID tracks frequently used, long-term data blocks and copies them to a dedicated partition spread across all the disks in the array. When new disks are added, CRAID only needs to extend this process to the new devices to redistribute this partition, thus greatly reducing the overhead of the upgrade process. In addition, the reorganized access patterns within this partition improve the array’s performance, amortizing the copy overhead and allowing CRAID to offer a performance competitive with traditional RAIDs. We describe CRAID’s motivation and design and we evaluate it by replaying seven real-world workloads including a file server, a web server and a user share. Our experiments show that CRAID can successfully detect hot data variations and begin using new disks as soon as they are added to the array. Also, the usage of a dedicated partition improves the sequentiality of relevant data access, which amortizes the cost of reorganizations. Finally, we prove that a full-HDD CRAID array with a small distributed partition (<1.28% per disk) can compete in performance with an ideally restriped RAID-5 and a hybrid RAID-5 with a small SSD cache.Peer ReviewedPostprint (published version

The Limits of In-run Calibration of MEMS and the Effect of New Techniques

Inertial sensors can significantly increase the robustness of an integrated navigation system by bridging gaps in the coverage of other positioning technologies, such as GNSS or Wi-Fi positioning [1]. A full set of chip-scale MEMS accelerometers and gyros can now be bought for less than $10, potentially opening up a wide range of new applications. However, these sensors require calibration before they can be used for navigation[2]. Higher quality inertial sensors may be calibrated “in-run” using Kalman filter-based estimation as part of their integration with GNSS or other position-fixing techniques. However, this approach can fail when applied to sensors with larger errors which break the Kalman filter due to the linearity and small-angle approximations within its system model not being valid. Possible solutions include: replacing the Kalman filter with a non-linear estimation algorithm, a pre-calibration procedure and smart array [3]. But these all have costs in terms of user effort, equipment or processing load. This paper makes two key contributions to knowledge. Firstly, it determines the maximum tolerable sensor errors for any in-run calibration technique using a basic Kalman filter by developing clear criteria for filter failure and performing Monte-Carlo simulations for a range of different sensor specifications. Secondly, it assesses the extent to which pre-calibration and smart array techniques enable Kalman filter-based in-run calibration to be applied to lower-quality sensors. Armed with this knowledge of the Kalman filter’s limits, the community can avoid both the unnecessary design complexity and computational power consumption caused by over-engineering the filter and the poor navigation performance that arises from an inadequate filter. By establishing realistic limits, one can determine whether real sensors are suitable for in-run calibration with simple characterization tests, rather than having to perform time-consuming empirical testing

A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multi-core neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.Comment: 17 pages, 14 figure

A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS

In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-μm SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 μm wide, 10 mm long, 20 μm thick), achieving a crosstalk of −64.4 dB. The probe base (5 × 9 mm2) implements dual-band recording and a 1

A dynamic Bayesian nonlinear mixed-effects model of HIV response incorporating medication adherence, drug resistance and covariates

HIV dynamic studies have contributed significantly to the understanding of HIV pathogenesis and antiviral treatment strategies for AIDS patients. Establishing the relationship of virologic responses with clinical factors and covariates during long-term antiretroviral (ARV) therapy is important to the development of effective treatments. Medication adherence is an important predictor of the effectiveness of ARV treatment, but an appropriate determinant of adherence rate based on medication event monitoring system (MEMS) data is critical to predict virologic outcomes. The primary objective of this paper is to investigate the effects of a number of summary determinants of MEMS adherence rates on virologic response measured repeatedly over time in HIV-infected patients. We developed a mechanism-based differential equation model with consideration of drug adherence, interacted by virus susceptibility to drug and baseline characteristics, to characterize the long-term virologic responses after initiation of therapy. This model fully integrates viral load, MEMS adherence, drug resistance and baseline covariates into the data analysis. In this study we employed the proposed model and associated Bayesian nonlinear mixed-effects modeling approach to assess how to efficiently use the MEMS adherence data for prediction of virologic response, and to evaluate the predicting power of each summary metric of the MEMS adherence rates.Comment: Published in at http://dx.doi.org/10.1214/10-AOAS376 the Annals of Applied Statistics (http://www.imstat.org/aoas/) by the Institute of Mathematical Statistics (http://www.imstat.org

Security of GPS/INS based On-road Location Tracking Systems

Location information is critical to a wide-variety of navigation and tracking applications. Today, GPS is the de-facto outdoor localization system but has been shown to be vulnerable to signal spoofing attacks. Inertial Navigation Systems (INS) are emerging as a popular complementary system, especially in road transportation systems as they enable improved navigation and tracking as well as offer resilience to wireless signals spoofing, and jamming attacks. In this paper, we evaluate the security guarantees of INS-aided GPS tracking and navigation for road transportation systems. We consider an adversary required to travel from a source location to a destination, and monitored by a INS-aided GPS system. The goal of the adversary is to travel to alternate locations without being detected. We developed and evaluated algorithms that achieve such goal, providing the adversary significant latitude. Our algorithms build a graph model for a given road network and enable us to derive potential destinations an attacker can reach without raising alarms even with the INS-aided GPS tracking and navigation system. The algorithms render the gyroscope and accelerometer sensors useless as they generate road trajectories indistinguishable from plausible paths (both in terms of turn angles and roads curvature). We also designed, built, and demonstrated that the magnetometer can be actively spoofed using a combination of carefully controlled coils. We implemented and evaluated the impact of the attack using both real-world and simulated driving traces in more than 10 cities located around the world. Our evaluations show that it is possible for an attacker to reach destinations that are as far as 30 km away from the true destination without being detected. We also show that it is possible for the adversary to reach almost 60-80% of possible points within the target region in some cities

Maximum Effectiveness of Electrostatic Energy Harvesters When Coupled to Interface Circuits

Accepted versio

Limits on Fundamental Limits to Computation

An indispensable part of our lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the last fifty years. Such Moore scaling now requires increasingly heroic efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and enrich our understanding of integrated-circuit scaling, we review fundamental limits to computation: in manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, we recall how some limits were circumvented, compare loose and tight limits. We also point out that engineering difficulties encountered by emerging technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl