Overview of Hydra: a concurrent language for synchronous digital circuit design

Hydra is a computer hardware description language that integrates several kinds of software tool (simulation, netlist generation and timing analysis) within a single circuit specification. The design language is inherently concurrent, and it offers black box abstraction and general design patterns that simplify the design of circuits with regular structure. Hydra specifications are concise, allowing the complete design of a computer system as a digital circuit within a few pages. This paper discusses the motivations behind Hydra, and illustrates the system with a significant portion of the design of a basic RISC processor

Option Pricing using Quantum Computers

We present a methodology to price options and portfolios of options on a gate-based quantum computer using amplitude estimation, an algorithm which provides a quadratic speedup compared to classical Monte Carlo methods. The options that we cover include vanilla options, multi-asset options and path-dependent options such as barrier options. We put an emphasis on the implementation of the quantum circuits required to build the input states and operators needed by amplitude estimation to price the different option types. Additionally, we show simulation results to highlight how the circuits that we implement price the different option contracts. Finally, we examine the performance of option pricing circuits on quantum hardware using the IBM Q Tokyo quantum device. We employ a simple, yet effective, error mitigation scheme that allows us to significantly reduce the errors arising from noisy two-qubit gates.Comment: Fixed a typo. This article has been accepted in Quantu

2D Qubit Placement of Quantum Circuits using LONGPATH

In order to achieve speedup over conventional classical computing for finding solution of computationally hard problems, quantum computing was introduced. Quantum algorithms can be simulated in a pseudo quantum environment, but implementation involves realization of quantum circuits through physical synthesis of quantum gates. This requires decomposition of complex quantum gates into a cascade of simple one qubit and two qubit gates. The methodological framework for physical synthesis imposes a constraint regarding placement of operands (qubits) and operators. If physical qubits can be placed on a grid, where each node of the grid represents a qubit then quantum gates can only be operated on adjacent qubits, otherwise SWAP gates must be inserted to convert non-Linear Nearest Neighbor architecture to Linear Nearest Neighbor architecture. Insertion of SWAP gates should be made optimal to reduce cumulative cost of physical implementation. A schedule layout generation is required for placement and routing apriori to actual implementation. In this paper, two algorithms are proposed to optimize the number of SWAP gates in any arbitrary quantum circuit. The first algorithm is intended to start with generation of an interaction graph followed by finding the longest path starting from the node with maximum degree. The second algorithm optimizes the number of SWAP gates between any pair of non-neighbouring qubits. Our proposed approach has a significant reduction in number of SWAP gates in 1D and 2D NTC architecture.Comment: Advanced Computing and Systems for Security, SpringerLink, Volume 1

Newark College of Engineering Graduate Programs 1970-71 Academic Year

https://digitalcommons.njit.edu/coursecatalogs/1025/thumbnail.jp

In-situ resonant band engineering of solution-processed semiconductors generates high performance n-type thermoelectric nano-inks.

Thermoelectric devices possess enormous potential to reshape the global energy landscape by converting waste heat into electricity, yet their commercial implementation has been limited by their high cost to output power ratio. No single "champion" thermoelectric material exists due to a broad range of material-dependent thermal and electrical property optimization challenges. While the advent of nanostructuring provided a general design paradigm for reducing material thermal conductivities, there exists no analogous strategy for homogeneous, precise doping of materials. Here, we demonstrate a nanoscale interface-engineering approach that harnesses the large chemically accessible surface areas of nanomaterials to yield massive, finely-controlled, and stable changes in the Seebeck coefficient, switching a poor nonconventional p-type thermoelectric material, tellurium, into a robust n-type material exhibiting stable properties over months of testing. These remodeled, n-type nanowires display extremely high power factors (~500 µW m-1K-2) that are orders of magnitude higher than their bulk p-type counterparts