Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology

It is well known that high-energy particle strikes on an integrated circuit can cause circuit errors. We quantify the fraction of a layout which is susceptible to multiple transients, through the notion of critical area fraction (CAF). We perform a 2D-study on a layout of 65 nm planar transistors to evaluate maximum values of CAF. We find that CAF can be as high as 1, that is, 100% of the layout area is vulnerable. Potentials of adjacent source/drain regions play a significant role in increasing the CAF and simple layout techniques do not reduce the CAF substantially. We confirm these observations through 3D simulations of inverter layouts. A key observation is that, CAF is high in the region of the layout which contains small gates. At the circuit-level, multiple transients not only cause multiple errors, they also merge to create wider transient increasing its capture probability. A circuit-aware placement of vulnerable gates and alternate latch designs may be required to alleviate the problem

Data for: Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology

This repository contains the device simulation raw data of 65nm planar transistors (2D and 3D) : device command files simulation template and csv files, python scripts to run the Sentaurus device simulations and analyze the data Python scripts have description inside them on how to use them Commands: Tool Sentaurus Structure editor: sde - to make the device- sde -e Or copy- paste the commands in the command window after opening sde Once the device is made, Build mesh - to obtain tdr. Tdr will be used to run sdevice simulation sdevice - to run simulation svisual & - to view the device inspect & - to view current or transient plots Scripts written by me to automate Python_generate_sdevice_runsim.py or python_current.py needs to be copied in every folder where the sdevice command files need to be generated. It takes a template file as input and a csv file having different parameters as another input. It generates sdev files and runs sim Python_runboth.py - combines both python_post-process_250p_limit.py and python_combine_2csv.py. The first one extracts charge values from the plt files. The second one, combines the input csv file and this charge values column by column. Or copy- paste the commands in the command window after opening sde Once the device is made, Build mesh - to obtain tdr. Tdr will be used to run sdevice simulation Contact me at: [email protected] (available temporarily) or at [email protected] Dept of EE, IIT Bombay, Mumbai, Indi