Analysis of Quasi-Cyclic LDPC codes under ML decoding over the erasure channel

In this paper, we show that Quasi-Cyclic LDPC codes can efficiently accommodate the hybrid iterative/ML decoding over the binary erasure channel. We demonstrate that the quasi-cyclic structure of the parity-check matrix can be advantageously used in order to significantly reduce the complexity of the ML decoding. This is achieved by a simple row/column permutation that transforms a QC matrix into a pseudo-band form. Based on this approach, we propose a class of QC-LDPC codes with almost ideal error correction performance under the ML decoding, while the required number of row/symbol operations scales as $k\sqrt{k}$, where $k$ is the number of source symbols.Comment: 6 pages, ISITA1

Gurafu hyogen o riyoshita ayamari teisei hoshiki no kosei ni kansuru kenkyu

制度:新 ; 報告番号:乙2221号 ; 学位の種類:博士(工学) ; 授与年月日:2009/3/24 ; 早大学位記番号:新508

Myths and Realities of Rateless Coding

Fixed-rate and rateless channel codes are generally treated separately in the related research literature and so, a novice in the field inevitably gets the impression that these channel codes are unrelated. By contrast, in this treatise, we endeavor to further develop a link between the traditional fixed-rate codes and the recently developed rateless codes by delving into their underlying attributes. This joint treatment is beneficial for two principal reasons. First, it facilitates the task of researchers and practitioners, who might be familiar with fixed-rate codes and would like to jump-start their understanding of the recently developed concepts in the rateless reality. Second, it provides grounds for extending the use of the well-understood code design tools — originally contrived for fixed-rate codes — to the realm of rateless codes. Indeed, these versatile tools proved to be vital in the design of diverse fixed-rate-coded communications systems, and thus our hope is that they will further elucidate the associated performance ramifications of the rateless coded schemes

Polynomials in Error Detection and Correction in Data Communication System

The chapter gives an overview of the various types of errors encountered in a communication system. It discusses the various error detection and error correction codes. The role of polynomials in error detection and error correction is discussed in detail with the architecture for practical implementation of the codes in a communication channel

Luby Transform Coding Aided Bit-Interleaved Coded Modulation for the Wireless Internet

Bit-Interleaved Coded Modulation using Iterative Decoding (BICM-ID) is amalgamated with Luby Transform (LT) coding. The resultant joint design of the physical and data link layer substantially improves the attainable Bit Error Rate (BER) performance. A Cyclic Redundancy Check (CRC) combined with a novel Log-Likelihood Ratio (LLR) based packet reliability estimation method is proposed for the sake of detecting and disposing of erroneous packets. Subsequently, bit-by-bit LT decoding is proposed, which facilitates a further BER improvement at a lower number of BICM-ID iterations. Finally, we revisit the pseudo random generator function used for designing the LT generator matrix

Spinal codes

Spinal codes are a new class of rateless codes that enable wireless networks to cope with time-varying channel conditions in a natural way, without requiring any explicit bit rate selection. The key idea in the code is the sequential application of a pseudo-random hash function to the message bits to produce a sequence of coded symbols for transmission. This encoding ensures that two input messages that differ in even one bit lead to very different coded sequences after the point at which they differ, providing good resilience to noise and bit errors. To decode spinal codes, this paper develops an approximate maximum-likelihood decoder, called the bubble decoder, which runs in time polynomial in the message size and achieves the Shannon capacity over both additive white Gaussian noise (AWGN) and binary symmetric channel (BSC) models. Experimental results obtained from a software implementation of a linear-time decoder show that spinal codes achieve higher throughput than fixed-rate LDPC codes, rateless Raptor codes, and the layered rateless coding approach of Strider, across a range of channel conditions and message sizes. An early hardware prototype that can decode at 10 Mbits/s in FPGA demonstrates that spinal codes are a practical construction.Massachusetts Institute of Technology (Irwin and Joan Jacobs Presidential Fellowship)Massachusetts Institute of Technology (Claude E. Shannon Assistantship)Intel Corporation (Intel Fellowship