Sparse distributed memory prototype: Principles of operation

Sparse distributed memory is a generalized random access memory (RAM) for long binary words. Such words can be written into and read from the memory, and they can be used to address the memory. The main attribute of the memory is sensitivity to similarity, meaning that a word can be read back not only by giving the original right address but also by giving one close to it as measured by the Hamming distance between addresses. Large memories of this kind are expected to have wide use in speech and scene analysis, in signal detection and verification, and in adaptive control of automated equipment. The memory can be realized as a simple, massively parallel computer. Digital technology has reached a point where building large memories is becoming practical. The research is aimed at resolving major design issues that have to be faced in building the memories. The design of a prototype memory with 256-bit addresses and from 8K to 128K locations for 256-bit words is described. A key aspect of the design is extensive use of dynamic RAM and other standard components

The Generic Checkout System Approach to Ground Checkout Systems

With the advent of the Space Station, Heavy Lift Launch Vehicle and other projects, NASA has been prompted to critique major ground checkout systems around KSC. This critique is being used as a basis for the development of a central set of functions which are common to all checkout operations throughout the program. A prototyping effort was started over a year ago to implement those central functions, this effort was called the Generic Checkout System(GCS) which, over the past year, has grown into a working model 1 for ground checkout systems. At the Twenty-Third Space Congress a paper was presented which outlined the rudimentary operations of the GCS. Since that time GCS has evolved into a state of the art checkout system which demonstrates flexibility and ease of use. The GCS system has been chosen as the architecture which will support the Partial Paylod Checkout Unit(PPCU), a new system to be installed in early 1990. The development of the GCS system was meant to also address several problems inherent in current checkout systems: lack of flexibility, poor user interfaces and the abscence of an upgrade path from obsolete hardware. The GCS seeks to solve these problems in ways which utilize high technology advances in computer hardware and software. These advances include the use of commercial UNIX operating system based computers which offer vendor independence and portability of software, the use of state of the art user interfaces offering high resolution graphics, mouse interfaces and the ability to create displays interactively without the need to generate code to drive them. The use of other high tech products is also apparent in the GCS such as the support for Artificial intelligence, relational data base technologies, ADA programming language, parallel processing, RISC technology architectures, optical storage media, Local Area Network Connectivity, commercial graphics packages, INMOS transputers and the latest microprocessor technologies. This paper will attempt to explore some of the facets of the GCS prototyping and development effort and mention the future plans for the architecture which has been developed

A Method of Fast Data Transfer From FASTBUS

One major factor which affects the counting efficiency of a nuclear physics experiment is the dead time of the detectors and the data acquisition system. Experiments performed by Glasgow University photonuclear group typically involve the readout of ~ 1000 ADC's and ~ 1000 scalers which contain information on the products of a photo-disintegration event. These require fast readout to minimise dead time and to this end a method of programming the model 1821 FASTBUS Segment Management Interface (SMI) to increase data throughput coming from FASTBUS has been developed. The electronic hardware used is comprised of VMDE-bus, CAMAC, and FASTBUS systems. The VME-based CPU is the heart of the data acquisition system. FASTBUS is mainly used for ADC's and TDC's while CAMAC is mostly used to control the experimental parameters such as detector thresholds, trigger logic, high voltage etc. Each FASTBUS crate is controlled by a LeCroy 1821 Segment Manager Interface (SMI), and the interfacing to the VME CPU is accomplished either by using the VME fast memory module type HSM8170 or the slower CAMAC interface type LeCroy 2891A. The HSM8170 is connected to the SMI using the 32-bit LeCroy ECL bus. The VME CPU runs the OS9 operating system, and the data acquisition software has been written almost entirely in C. Software for the sequencer in the 1821 SMI is written in machine code, although it is hoped in the future to develop a simple assembler. Two different SMI codes have been developed. These are called CODE1 and CODE2. The first attempt, CODE1, uses the slow, CAMAC connection at the front panel of the 1821 SMI for module initialisation and data readout. To improve the data throughput, it was decided to develop CODE2 which uses the rear panel ECL bus connection to a fast VME memory, and require no intervention from the VME host CPU to initiate data readout. Associated C routines written for the VME CPU handle downloading of the code to the SMI and create FASTBUS module addressing SMI instruction words. Finally, the performance of the two FASTBUS readout methods has been compared on a test setup where more than 100 ADC channels are read for each event. Under these conditions, the dead time for a CODE2 readout was found to be approximately a factor of 8 less the dead time for CODE1

GRAPHICAL CONFIGURATION PROGRAMMING - THE STRUCTURAL DESCRIPTION, CONSTRUCTION AND EVOLUTION OF SOFTWARE SYSTEMS USING GRAPHICS

Published versio

Computer hardware and software for robotic control

The KSC has implemented an integrated system that coordinates state-of-the-art robotic subsystems. It is a sensor based real-time robotic control system performing operations beyond the capability of an off-the-shelf robot. The integrated system provides real-time closed loop adaptive path control of position and orientation of all six axes of a large robot; enables the implementation of a highly configurable, expandable testbed for sensor system development; and makes several smart distributed control subsystems (robot arm controller, process controller, graphics display, and vision tracking) appear as intelligent peripherals to a supervisory computer coordinating the overall systems

The Condor Programmer's Manual - Version II

This is the CONDOR programmer's manual, that describes the hardware and software that form the basis of the real-time computational architecture built originally for the Utah-MIT hand. The architecture has been used successfully to control the hand and the MIT-Serial Link Direct Drive Arm in the past. A number of such systems are being built to address the computational needs of other robotics research efforts in and around the lab. This manual, which is intended primarily for programmers/users of the CONDOR system, represents our effort at documenting the system so that it can be a generally useful research tool.MIT Artificial Intelligence Laborator

OKI advanced array processor (AAP) hardware description

Bruce R. Musicus and Srinivasa Prasanna