802 research outputs found
Comparative Study of Various Systems on Chips Embedded in Mobile Devices
Systems-on-chips (SoCs) are the latest incarnation of very large scale integration (VLSI) technology. A single integrated circuit can contain over 100 million transistors. Harnessing all this computing power requires designers to move beyond logic design into computer architecture, meet real-time deadlines, ensure low-power operation, and so on. These opportunities and challenges make SoC design an important field of research. So in the paper we will try to focus on the various aspects of SOC and the applications offered by it. Also the different parameters to be checked for functional verification like integration and complexity are described in brief. We will focus mainly on the applications of system on chip in mobile devices and then we will compare various mobile vendors in terms of different parameters like cost, memory, features, weight, and battery life, audio and video applications. A brief discussion on the upcoming technologies in SoC used in smart phones as announced by Intel, Microsoft, Texas etc. is also taken up. Keywords: System on Chip, Core Frame Architecture, Arm Processors, Smartphone
Prevention of Drug Use and Treatment of Drug Use Disorders in Rural Settings
This Guide on Prevention of Drug Use and Treatment of Drug Use Disorders in Rural Settings was prepared by the United Nations Office on Drugs and Crime (UNODC) Drug Prevention and Health Branch (DHB), in the context of the global project Treatnet II: OFID-UNODC Programme to prevent HIV/AIDS through Treatnet Phase II, with the aim of providing an awareness-raising tool and guidance for policymakers, public health officials, local authorities and other stakeholders in dealing with substance use issues in rural settings in their respective countries. This Guide will serve as an awareness-raising tool and guidance for policymakers, public health officials, local authorities and other stakeholders in dealing with substance use issues in rural settings in their respective countries. It will “set the stage” for the identification, assessment, planning and implementation of both prevention interventions and policies, as well as interventions targeting rural drug users, by: Describing substance use problems in rural settings and factors contributing to them. Identifying tools that can be used to assess the scope of rural substance use in their countries. Describing evidence-based prevention, treatment and recovery strategies that can be implemented in rural areas. Providing examples of successful promising and evidence-based strategies implemented in diverse rural areas worldwide.
This Guide is intended to be shared widely with policymakers and other stakeholders concerned with the problems of substance use in rural settings. It provides an understanding of several key economic and social disparities driving rural substance use and the barriers to treatment experienced by rural people with substance use disorders
Continuous Integration for Fast SoC Algorithm Development
Digital systems have become advanced, hard to design and optimize due to ever-growing technology. Integrated Circuits (ICs) have become more complicated due to complex computations in latest technologies. Communication systems such as mobile networks have evolved and become a part of our daily lives with the advancement in technology over the years. Hence, need of efficient, reusable and automated processes for System-on-a-Chip (SoC) development has been increased. Purpose of this thesis is to study and evaluate currently used SoC development processes and presents guidelines on how these processes can be streamlined.
The thesis starts by evaluating currently used SoC development flows and their advantages and disadvantages. One important aspect is to identify step which cause duplication of work and unnecessary idle times in SoC development teams. A study is conducted and input from SoC development experts is taken in order to optimize SoC flows and use of Continuous Integration (CI) system. An algorithm model is implemented that can be used in multiple stages of SoC development at adequate complexity and is “easy enough” to be used for a person not mastering the topic. The thesis outcome is proposal for CI system in SoC development for accelerating the speed and reliability of implementing algorithms to RTL code and finally into product. CI system tool is also implemented to automate and test the model design so that it also remains up to date
Improving Mobile SOC\u27s Performance as an Energy Efficient DSP Platform with Heterogeneous Computing
Mobile system-on-chip (SOC) technology is improving at a staggering rate spurred primarily by the adoption of smartphones and tablets. This rapid innovation has allowed the mobile SOC to be considered in everything from high performance computing to embedded applications. In this work, modern SOC\u27s heterogeneous computing capabilities are evaluated with a focus toward digital signal processing (DSP). Evaluation is conducted on modern consumer devices running Android operating system and leveraging the relatively new RenderScript Compute to utilize CPU resources alongside other compute resources such as graphics processing units (GPUs) and digital signal processors. In order to benchmark these concepts, several implementations of both the discrete Fourier transform (DFT) and the fast Fourier transform (FFT) are tested across devices. The results show both improvement in performance and energy efficiency on many devices compared to traditional Java implementations and indicate that the mobile SOC is a relevant platform for DSP applications
Unified System on Chip RESTAPI Service (USOCRS)
Abstract. This thesis investigates the development of a Unified System on Chip RESTAPI Service (USOCRS) to enhance the efficiency and effectiveness of SOC verification reporting. The research aims to overcome the challenges associated with the transfer, utilization, and interpretation of SoC verification reports by creating a unified platform that integrates various tools and technologies.
The research methodology used in this study follows a design science approach. A thorough literature review was conducted to explore existing approaches and technologies related to SOC verification reporting, automation, data visualization, and API development. The review revealed gaps in the current state of the field, providing a basis for further investigation. Using the insights gained from the literature review, a system design and implementation plan were developed. This plan makes use of cutting-edge technologies such as FASTAPI, SQL and NoSQL databases, Azure Active Directory for authentication, and Cloud services. The Verification Toolbox was employed to validate SoC reports based on the organization’s standards. The system went through manual testing, and user satisfaction was evaluated to ensure its functionality and usability.
The results of this study demonstrate the successful design and implementation of the USOCRS, offering SOC engineers a unified and secure platform for uploading, validating, storing, and retrieving verification reports. The USOCRS facilitates seamless communication between users and the API, granting easy access to vital information including successes, failures, and test coverage derived from submitted SoC verification reports. By automating and standardizing the SOC verification reporting process, the USOCRS eliminates manual and repetitive tasks usually done by developers, thereby enhancing productivity, and establishing a robust and reliable framework for report storage and retrieval. Through the integration of diverse tools and technologies, the USOCRS presents a comprehensive solution that adheres to the required specifications of the SOC schema used within the organization.
Furthermore, the USOCRS significantly improves the efficiency and effectiveness of SOC verification reporting. It facilitates the submission process, reduces latency through optimized data storage, and enables meaningful extraction and analysis of report data
Energy reconstruction on the LHC ATLAS TileCal upgraded front end: feasibility study for a sROD co-processing unit
Dissertation presented in ful lment of the requirements for the degree of:
Master of Science in Physics
2016The Phase-II upgrade of the Large Hadron Collider at CERN in the early 2020s
will enable an order of magnitude increase in the data produced, unlocking the
potential for new physics discoveries. In the ATLAS detector, the upgraded Hadronic
Tile Calorimeter (TileCal) Phase-II front end read out system is currently being
prototyped to handle a total data throughput of 5.1 TB/s, from the current 20.4 GB/s.
The FPGA based Super Read Out Driver (sROD) prototype must perform an energy
reconstruction algorithm on 2.88 GB/s raw data, or 275 million events per second.
Due to the very high level of pro ciency required and time consuming nature of
FPGA rmware development, it may be more e ective to implement certain complex
energy reconstruction and monitoring algorithms on a general purpose, CPU based
sROD co-processor. Hence, the feasibility of a general purpose ARM System on Chip
based co-processing unit (PU) for the sROD is determined in this work.
A PCI-Express test platform was designed and constructed to link two ARM
Cortex-A9 SoCs via their PCI-Express Gen-2 x1 interfaces. Test results indicate that
the latency of the PCI-Express interface is su ciently low and the data throughput is
superior to that of alternative interfaces such as Ethernet, for use as an interconnect
for the SoCs to the sROD. CPU performance benchmarks were performed on ve ARM
development platforms to determine the CPU integer,
oating point and memory
system performance as well as energy e ciency. To complement the benchmarks,
Fast Fourier Transform and Optimal Filtering (OF) applications were also tested.
Based on the test results, in order for the PU to process 275 million events per
second with OF, within the 6 s timing budget of the ATLAS triggering system, a
cluster of three Tegra-K1, Cortex-A15 SoCs connected to the sROD via a Gen-2 x8
PCI-Express interface would be suitable. A high level design for the PU is proposed
which surpasses the requirements for the sROD co-processor and can also be used
in a general purpose, high data throughput system, with 80 Gb/s Ethernet and
15 GB/s PCI-Express throughput, using four X-Gene SoCs
SOC ATTACKER CENTRIC - Analysis of a prevention oriented SOC
This thesis will explain what a Security Operation Center (SOC) is and how it works,
analyzing all the different phases and modules that make up the final product. Typically,
a SOC centralizes all of the company’s information in one place where it can
constantly keep an eye on the data and monitor the system. The IT infrastructure
is analyzed in real time for anomalies, malicious activities, or intrusion attempts.
Not only the data sent from one machine to another, but also the physical state
and resources (e.g., memory and CPU) are constantly monitored. Through the creation
and use of multiple detection rules, various alerts are generated and are then
reviewed by the SOC analyst team, which promptly informs customers in case of
need.
The State of the Art will be explored to study current SOCs and best practices
adopted. Then the innovative SOC Attacker Centric developed by the company
Wuerth Phoenix will be analyzed. The functioning of the SOC-AC will be studied
and explained, highlighting how it adds to the classic suite of services offered by a
SOC an extra part, focused on the attacker’s point of view. This SOC-AC is capable
of covering the reconnaissance phase, usually neglected by SOCs, in which attackers
gather information about a target in order to find the best strategy to break in and
successfully carry out the attack.
In the last part of the thesis, the design and implementation of an automatic SOC
reporting functionality will be shown. An important feature is to have an efficient
communication channel with the customer and to provide them with data on the
status of the SOC they are paying for. Initially, this procedure was a static, manually
executed, error-prone process. The procedure was improved by creating a
semi-automatic system of report generation and delivery using the Elastic SIEM
and several languages such as python, bash, Lucene, Elastic, and Kibana Query
Languages, leaving the reporter with fewer parts to analyze and document, saving
time and resources
Internationalisation of Innovation: Why Chip Design Moving to Asia
This paper will appear in International Journal of Innovation Management, special issue in honor of Keith Pavitt, (Peter Augsdoerfer, Jonathan Sapsed, and James Utterback, guest editors), forthcoming. Among Keith Pavitt's many contributions to the study of innovation is the proposition that physical proximity is advantageous for innovative activities that involve highly complex technological knowledge But chip design, a process that creates the greatest value in the electronics industry and that requires highly complex knowledge, is experiencing a massive dispersion to leading Asian electronics exporting countries. To explain why chip design is moving to Asia, the paper draws on interviews with 60 companies and 15 research institutions that are doing leading-edge chip design in Asia. I demonstrate that "pull" and "policy" factors explain what attracts design to particular locations. But to get to the root causes that shift the balance in favor of geographical decentralization, I examine "push" factors, i.e. changes in design methodology ("system-on-chip design") and organization ("vertical specialization" within global design networks). The resultant increase in knowledge mobility explains why chip design - that, in Pavitt's framework is not supposed to move - is moving from the traditional centers to a few new specialized design clusters in Asia. A completely revised and updated version has been published as: " Complexity and Internationalisation of Innovation: Why is Chip Design Moving to Asia?," in International Journal of Innovation Management, special issue in honour of Keith Pavitt, Vol. 9,1: 47-73.
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