Hierarchical probabilistic macromodeling for QCA circuits

With the goal of building an hierarchical design methodology for quantum-dot cellular automata (QCA) circuits, we put forward a novel, theoretically sound, method for abstracting the behavior of circuit components in QCA circuit, such as majority logic, lines, wire-taps, cross-overs, inverters, and corners, using macromodels. Recognizing that the basic operation of QCA is probabilistic in nature, we propose probabilistic macromodels for standard QCA circuit elements based on conditional probability characterization, defined over the output states given the input states. Any circuit model is constructed by chaining together the individual logic element macromodels, forming a Bayesian network, defining a joint probability distribution over the whole circuit. We demonstrate three uses for these macromodel-based circuits. First, the probabilistic macromodels allow us to model the logical function of QCA circuits at an abstract level - the "circuit" level - above the current practice of layout level in a time and space efficient manner. We show that the circuit level model is orders of magnitude faster and requires less space than layout level models, making the design and testing of large QCA circuits efficient and relegating the costly full quantum-mechanical simulation of the temporal dynamics to a later stage in the design process. Second, the probabilistic macromodels abstract crucial device level characteristics such as polarization and low-energy error state configurations at the circuit level. We demonstrate how this macromodel-based circuit level representation can be used to infer the ground state probabilities, i.e., cell polarizations, a crucial QCA parameter. This allows us to study the thermal behavior of QCA circuits at a higher level of abstraction. Third, we demonstrate the use of these macromodels for error analysis. We show that low-energy state configurations of the macromodel circuit match those of the layout level, thus allowing us to isolate weak p- oints in circuits design at the circuit level itsel

Bayesian macromodeling for circuit level QCA design

We present a probabilistic methodology to model and abstract the behavior of quantum-dot cellular automata circuit(QCA) at “ circuit level” above the current practice of layout level. These macromodels provide input-output relationship of components (a set of QCA cells emulating a logical function) that are faithful to the underlying quantum effects. We show the macromodeling of a few key circuit components in QCA circuit, such as majority logic, lines, wire-taps, cross-overs, inverters, and corners. In this work, we demostrate how we can make use of these macromodels to abstract the logical function of QCA circuits and to extract crucial device level characteristics such as polarization and low-energy error state configurations by circuit level Bayesian model, accurately accounting for temperature and other device level parameters. We also demonstrate how this macromodel based design can be used effectively in analysing and isolating the weak spots in the design at circuit level itself

Redundant Logic Insertion and Fault Tolerance Improvement in Combinational Circuits

This paper presents a novel method to identify and insert redundant logic into a combinational circuit to improve its fault tolerance without having to replicate the entire circuit as is the case with conventional redundancy techniques. In this context, it is discussed how to estimate the fault masking capability of a combinational circuit using the truth-cum-fault enumeration table, and then it is shown how to identify the logic that can introduced to add redundancy into the original circuit without affecting its native functionality and with the aim of improving its fault tolerance though this would involve some trade-off in the design metrics. However, care should be taken while introducing redundant logic since redundant logic insertion may give rise to new internal nodes and faults on those may impact the fault tolerance of the resulting circuit. The combinational circuit that is considered and its redundant counterparts are all implemented in semi-custom design style using a 32/28nm CMOS digital cell library and their respective design metrics and fault tolerances are compared

Probabilistic Circuit Architecture Using Statistical Learning

The main achievement of this project is the generalization of probabilistic circuit architecture. In other words, in mapping MRF into CMOS circuitry, one must fulfill two requirements; first bistable storage element for each logic state and second feedback network for belief propagation