Power-efficient layered Turbo Decoder processor

Turbo decoding offers' outstanding error correcting capabilities, that will be used in wireless applica- tions like the Universal Mobile Telecom Standard[4] (UMTS). However, the algorithm is very computational intensive, and therefore an implementation on a general purpose programmable DSP results' in a power consumption which reduces the applicability of turbo decoding in hand-heM applications. In this' paper we present a solution based on a layered processing architecture. This architecture includes an application specific Very Long Instruction Word (VLIW) processor, a data flow processor, and hardwired execution units' in a hierarchical way. The power consumption of this solution is an order of magnitude better than the implementation on a current state of the art, power efficient general purpose DSP