Exploration of photonic networks on chip with the University of Ferrara

Modern chips include several processors that communicate through an interconnection network, which has a direct impact on system performance, power consumption and chip area. Recent research points out the great potential of optical networks to reduce on-chip communication latency and energy. We plan to explore this state-of-the-art field during an internship in the University of Ferrara

Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors

There is still a significant gap between the optical network-on-chip (NoC) concept and a mature interconnect technology with practical relevance. Current research aims at bridging this gap by evolving basic optical components and by developing ad-hoc design tools to enable their use for system-level design. This paper points out another cause for the design predictability gap of optical NoC topologies, namely the physical placement of network interfaces in the target floorplan. Building on this awareness, the paper compares power efficiency of the most relevant topologies proposed so far for wavelength-routed optical NoCs in the context of a 3D-stacked multi-core processor