5,918 research outputs found
A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization
A new generation of radio telescopes is achieving unprecedented levels of
sensitivity and resolution, as well as increased agility and field-of-view, by
employing high-performance digital signal processing hardware to phase and
correlate large numbers of antennas. The computational demands of these imaging
systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the
number of independent beams, and N is the number of antennas. The
specifications of many new arrays lead to demands in excess of tens of PetaOps
per second.
To meet this challenge, we have developed a general purpose correlator
architecture using standard 10-Gbit Ethernet switches to pass data between
flexible hardware modules containing Field Programmable Gate Array (FPGA)
chips. These chips are programmed using open-source signal processing libraries
we have developed to be flexible, scalable, and chip-independent. This work
reduces the time and cost of implementing a wide range of signal processing
systems, with correlators foremost among them,and facilitates upgrading to new
generations of processing technology. We present several correlator
deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes
parameter application deployed on the Precision Array for Probing the Epoch of
Reionization.Comment: Accepted to Publications of the Astronomy Society of the Pacific. 31
pages. v2: corrected typo, v3: corrected Fig. 1
FPGA Design Techniques for Stable Cryogenic Operation
In this paper we show how a deep-submicron FPGA can be modified to operate at
extremely low temperatures through modifications in the supporting hardware and
in the firmware programming it. Though FPGAs are not designed to operate at a
few Kelvin, it is possible to do so on virtue of the extremely high doping
levels found in deep-submicron CMOS technology nodes. First, any PCB component,
that does not conform with this requirement, is removed. Both the majority of
decoupling capacitor types and voltage regulators are not well behaved at
cryogenic temperatures, asking for an ad-hoc solution to stabilize the FPGA
supply voltage, especially for sensitive applications. Therefore, we have
designed a firmware that enforces a constant power consumption, so as to
stabilize the supply voltage in the interior of the FPGA chip. The FPGA is
powered with a supply at several meters distance, causing significant IR drop
and thus fluctuations on the local supply voltage. To achieve the
stabilization, the variation in digital logic speed, which directly corresponds
to changes in supply voltage, is constantly measured and corrected for through
a tunable oscillator farm, implemented on the FPGA. The method is versatile and
robust, enabling seamless porting to other FPGA families and configurations.Comment: The following article has been submitted to Review of Scientific
Instruments. If it is published, it will be available on http://rsi.aip.or
Interfacing PDM sensors with PFM spiking systems: application for Neuromorphic Auditory Sensors
In this paper we present a sub-system to convert
audio information from low-power MEMS microphones with
pulse density modulation (PDM) output into rate coded spike
streams. These spikes represent the input signal of a Neuromorphic
Auditory Sensor (NAS), which is implemented with Spike
Signal Processing (SSP) building blocks. For this conversion, we
have designed a HDL component for FPGA able to interface
with PDM microphones and converts their pulses to temporal
distributed spikes following a pulse frequency modulation (PFM)
scheme with an accurate configurable Inter-Spike-Interval. The
new FPGA component has been tested in two scenarios, first as a
stand-alone circuit for its characterization, and then it has been
integrated with a full NAS design to verify its behavior. This
PDM interface demands less than 1% of a Spartan 6 FPGA
resources and has a power consumption below 5mW.Ministerio de Economía y Competitividad TEC2016-77785-
Enabling virtual radio functions on software defined radio for future wireless networks
Today's wired networks have become highly flexible, thanks to the fact that an increasing number of functionalities are realized by software rather than dedicated hardware. This trend is still in its early stages for wireless networks, but it has the potential to improve the network's flexibility and resource utilization regarding both the abundant computational resources and the scarce radio spectrum resources. In this work we provide an overview of the enabling technologies for network reconfiguration, such as Network Function Virtualization, Software Defined Networking, and Software Defined Radio. We review frequently used terminology such as softwarization, virtualization, and orchestration, and how these concepts apply to wireless networks. We introduce the concept of Virtual Radio Function, and illustrate how softwarized/virtualized radio functions can be placed and initialized at runtime, allowing radio access technologies and spectrum allocation schemes to be formed dynamically. Finally we focus on embedded Software-Defined Radio as an end device, and illustrate how to realize the placement, initialization and configuration of virtual radio functions on such kind of devices
A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS
In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-μm SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 μm wide, 10 mm long, 20 μm thick), achieving a crosstalk of −64.4 dB. The probe base (5 × 9 mm2) implements dual-band recording and a 1
- …