Jahresbericht 2013 zur kooperativen DV-Versorgung

:Vorwort ÜBERSICHT DER INSERENTEN 12 TEIL I ZUR ARBEIT DER DV-KOMMISSION 15 ZUR ARBEIT DES ERWEITERTEN IT-LENKUNGSAUSSCHUSSES 16 ZUR ARBEIT DES IT-LENKUNGSAUSSCHUSSES 17 ZUR ARBEIT DES WISSENSCHAFTLICHEN BEIRATES DES ZIH 17 TEIL II 1 DAS ZENTRUM FÜR INFORMATIONSDIENSTE UND HOCHLEISTUNGSRECHNEN (ZIH) 21 1.1 AUFGABEN 21 1.2 ZAHLEN UND FAKTEN (REPRÄSENTATIVE AUSWAHL) 21 1.3 HAUSHALT 22 1.4 STRUKTUR / PERSONAL 23 1.5 STANDORT 24 1.6 GREMIENARBEIT 25 2 KOMMUNIKATIONSINFRASTRUKTUR 27 2.1 NUTZUNGSÜBERSICHT NETZDIENSTE 27 2.2 NETZWERKINFRASTRUKTUR 27 2.3 KOMMUNIKATIONS- UND INFORMATIONSDIENSTE 37 3 ZENTRALE DIENSTANGEBOTE UND SERVER 47 3.1 SERVICE DESK 47 3.2 TROUBLE TICKET SYSTEM (OTRS) 48 3.3 NUTZERMANAGEMENT 49 3.4 LOGIN-SERVICE 50 3.5 BEREITSTELLUNG VON VIRTUELLEN SERVERN 51 3.6 STORAGE-MANAGEMENT 51 3.7 LIZENZ-SERVICE 57 3.8 PERIPHERIE-SERVICE 58 3.9 PC-POOLS 58 3.10 SECURITY 59 3.11 DRESDEN SCIENCE CALENDAR 60 4 SERVICELEISTUNGEN FÜR DEZENTRALE DV-SYSTEME 63 4.1 ALLGEMEINES 63 4.2 INVESTBERATUNG 63 4.3 PC SUPPORT 63 4.4 MICROSOFT WINDOWS-SUPPORT 64 4.5 ZENTRALE SOFTWARE-BESCHAFFUNG FÜR DIE TU DRESDEN 70 5 HOCHLEISTUNGSRECHNEN 73 5.1 HOCHLEISTUNGSRECHNER/SPEICHERKOMPLEX (HRSK-II) 73 5.2 NUTZUNGSÜBERSICHT DER HPC-SERVER 80 5.3 SPEZIALRESSOURCEN 81 5.4 GRID-RESSOURCEN 82 5.5 ANWENDUNGSSOFTWARE 84 5.6 VISUALISIERUNG 85 5.7 PARALLELE PROGRAMMIERWERKZEUGE 86 6 WISSENSCHAFTLICHE PROJEKTE, KOOPERATIONEN 89 6.1 „KOMPETENZZENTRUM FÜR VIDEOKONFERENZDIENSTE“ (VCCIV) 89 6.2 SKALIERBARE SOFTWARE-WERKZEUGE ZUR UNTERSTÜTZUNG DER ANWENDUNGSOPTIMIERUNG AUF HPC-SYSTEMEN 94 6.3 LEISTUNGS- UND ENERGIEEFFIZIENZ-ANALYSE FÜR INNOVATIVE RECHNERARCHITEKTUREN 96 6.4 DATENINTENSIVES RECHNEN, VERTEILTES RECHNEN UND CLOUD COMPUTING 100 6.5 DATENANALYSE, METHODEN UND MODELLIERUNG IN DEN LIFE SCIENCES 103 6.6 PARALLELE PROGRAMMIERUNG, ALGORITHMEN UND METHODEN 106 6.7 KOOPERATIONEN 111 7 AUSBILDUNGSBETRIEB UND PRAKTIKA 113 7.1 AUSBILDUNG ZUM FACHINFORMATIKER / FACHRICHTUNG ANWENDUNGSENTWICKLUNG 113 7.2 PRAKTIKA 114 8 AUS- UND WEITERBILDUNGSVERANSTALTUNGEN 115 9 VERANSTALTUNGEN 117 10 PUBLIKATIONEN 118 TEIL III BEREICH MATHEMATIK UND NATURWISSENSCHAFTEN 125 BEREICH GEISTES UND SOZIALWISSENSCHAFTEN 151 BEREICH INGENIEURWISSENSCHAFTEN 177 BEREICH BAU UND UMWELT 189 BEREICH MEDIZIN 223 ZENTRALE UNIVERSITÄTSVERWALTUNG 23

A Unified Infrastructure for Monitoring and Tuning the Energy Efficiency of HPC Applications

High Performance Computing (HPC) has become an indispensable tool for the scientific community to perform simulations on models whose complexity would exceed the limits of a standard computer. An unfortunate trend concerning HPC systems is that their power consumption under high-demanding workloads increases. To counter this trend, hardware vendors have implemented power saving mechanisms in recent years, which has increased the variability in power demands of single nodes. These capabilities provide an opportunity to increase the energy efficiency of HPC applications. To utilize these hardware power saving mechanisms efficiently, their overhead must be analyzed. Furthermore, applications have to be examined for performance and energy efficiency issues, which can give hints for optimizations. This requires an infrastructure that is able to capture both, performance and power consumption information concurrently. The mechanisms that such an infrastructure would inherently support could further be used to implement a tool that is able to do both, measuring and tuning of energy efficiency. This thesis targets all steps in this process by making the following contributions: First, I provide a broad overview on different related fields. I list common performance measurement tools, power measurement infrastructures, hardware power saving capabilities, and tuning tools. Second, I lay out a model that can be used to define and describe energy efficiency tuning on program region scale. This model includes hardware and software dependent parameters. Hardware parameters include the runtime overhead and delay for switching power saving mechanisms as well as a contemplation of their scopes and the possible influence on application performance. Thus, in a third step, I present methods to evaluate common power saving mechanisms and list findings for different x86 processors. Software parameters include their performance and power consumption characteristics as well as the influence of power-saving mechanisms on these. To capture software parameters, an infrastructure for measuring performance and power consumption is necessary. With minor additions, the same infrastructure can later be used to tune software and hardware parameters. Thus, I lay out the structure for such an infrastructure and describe common components that are required for measuring and tuning. Based on that, I implement adequate interfaces that extend the functionality of contemporary performance measurement tools. Furthermore, I use these interfaces to conflate performance and power measurements and further process the gathered information for tuning. I conclude this work by demonstrating that the infrastructure can be used to manipulate power-saving mechanisms of contemporary x86 processors and increase the energy efficiency of HPC applications