Investigation of the Timing Parameters of The Arbiter-Based Physically Unclonable Function Using a Ring Oscillator

Рассматривается возможность использования схемы кольцевого осциллятора для измерения задержек распространения сигналов через симметричные пути различных длин, реализованных на FPGA. Описывается создание экспериментальной установки и ход проведения экспериментов. Исследуется зависимость абсолютных значений задержек распространения сигналов и их статистических характеристик от количества блоков симметричных путей. Рассчитываются метрики стабильности и межкристальной уникальности на основе полученных экспериментальных данных измерений задержек. Подтверждается улучшение характеристик стабильности и уникальности значений задержек с увеличением длины симметричных путей АФНФ

Physical Unclonable Function Reliability on Reconfigurable Hardware and Reliability Degradation with Temperature and Supply Voltage Variations

A hardware security solution using a Physical Unclonable Function (PUF) is a promising approach to ensure security for physical systems. PUF utilizes the inherent instance-specific parameters of physical objects and it is evaluated based on the performance parameters such as uniqueness, reliability, randomness, and tamper evidence of the Challenge and Response Pairs (CRPs). These performance parameters are affected by operating conditions such as temperature and supply voltage variations. In addition, PUF implementation on Field Programmable Gate Array (FPGA) platform is proven to be more complicated than PUF implementation on Application-Specific Integrated Circuit (ASIC) technologies. The automatic placement and routing of logic cells in FPGA can affect the performance of PUFs due to path delay imbalance. In this work, the impact of power supply and temperature variations, on the reliability of an arbiter PUF is studied. Simulation results are conducted to determine the effects of these varying conditions on the CRPs. Simulation results show that ± 10% of power supply variation can affect the reliability of an arbiter PUF by about 51%, similarly temperature fluctuation between -40 0C and +60 0C reduces the PUF reliability by 58%. In addition, a new methodology to implement a reliable arbiter PUF on an FPGA platform is presented. Instead of using an extra delay measurement module, the Chip Planner tool for FPGA is used for manually placement to minimize the path delay misalignment to less than 8 ps