Resistive Switching in Silicon-rich Silicon Oxide

Over the recent decade, many different concepts of new emerging memories have been proposed. Examples of such include ferroelectric random access memories (FeRAMs), phase-change RAMs (PRAMs), resistive RAMs (RRAMs), magnetic RAMs (MRAMs), nano-crystal floating-gate flash memories, among others. The ultimate goal for any of these memories is to overcome the limitations of dynamic random access memories (DRAM) and flash memories. Non-volatile memories exploiting resistive switching – resistive RAM (RRAM) devices – offer the possibility of low programming energy per bit, rapid switching, and very high levels of integration – potentially in 3D. Resistive switching in a silicon-based material offers a compelling alternative to existing metal oxide-based devices, both in terms of ease of fabrication, but also in enhanced device performance. In this thesis I demonstrate a redox-based resistive switch exploiting the formation of conductive filaments in a bulk silicon-rich silicon oxide. My devices exhibit multi-level switching and analogue modulation of resistance as well as standard two-level switching. I demonstrate different operational modes (bipolar and unipolar switching modes) that make it possible to dynamically adjust device properties, in particular two highly desirable properties: non-linearity and self-rectification. Scanning tunnelling microscopy (STM), atomic force microscopy (AFM), and conductive atomic force microscopy (C-AFM) measurements provide a more detailed insight into both the location and the dimensions of the conductive filaments. I discuss aspects of conduction and switching mechanisms and we propose a physical model of resistive switching. I demonstrate room temperature quantisation of conductance in silicon oxide resistive switches, implying ballistic transport of electrons through a quantum constriction, associated with an individual silicon filament in the SiOx bulk. I develop a stochastic method to simulate microscopic formation and rupture of conductive filaments inside an oxide matrix. I use the model to discuss switching properties – endurance and switching uniformity

RRAM variability and its mitigation schemes

Emerging technologies such as RRAMs are attracting significant attention due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. However, critical causes of hardware reliability failures, such as process variation due to their nano-scale structure have gained considerable importance for acceptable memory yields. Such vulnerabilities make it essential to investigate new robust design strategies at the circuit system level. In this paper we have analyzed the RRAM variability phenomenon, its impact and variation tolerant techniques at the circuit level. Finally a variation-monitoring circuit is presented that discerns the reliable memory cells affected by process variability.Peer ReviewedPostprint (author's final draft

Controlled inter-state switching between quantized conductance states in resistive devices for multilevel memory

A detailed understanding of quantization conductance (QC), their correlation with resistive switching phenomena and controlled manipulation of quantized states is crucial for realizing atomic-scale multilevel memory elements. Here, we demonstrate highly stable and reproducible quantized conductance states (QC-states) in Al/Niobium oxide/Pt resistive switching devices. Three levels of control over the QC-states, required for multilevel quantized state memories, like, switching ON to different quantized states, switching OFF from quantized states, and controlled inter-state switching among one QC states to another has been demonstrated by imposing limiting conditions of stop-voltage and current compliance. The well defined multiple QC-states along with a working principle for switching among various states show promise for implementation of multilevel memory devices

Ion beam effect on Ge-Se chalcogenide glass films: Non-volatile memory array formation, structural changes and device performance

The conductive bridge non-volatile memory technology is an emerging way to replace traditional charge based memory devices for future neural networks and configurable logic applications. An array of the memory devices that fulfills logic operations must be developed for implementing such architectures. A scheme to fabricate these arrays, using ion bombardment through a mask, has been suggested and advanced by us. Performance of the memory devices is studied, based on the formation of vias and damage accumulation due to the interactions of Ar+ ions with GexSe1-x (x=0.2, 0.3 and 0.4) chalcogenide glasses as a function of the ion energy and dose dependence. Blanket films and devices were created to study the structural changes, surface roughness, and device performance. Raman Spectroscopy, Atomic Force Microscopy (AFM), Energy Dispersive X-Ray Spectroscopy (EDS) and electrical measurements expound the Ar+ ions behavior on thin films of GexSe1-x system. Raman studies show that there is a decrease in area ratio between edge-shared to corner-shared structural units, revealing occurrence of structural reorganization within the system as a result of ion/film interaction. AFM results demonstrate a tendency in surface roughness improvement with increased Ge concentration, after ion bombardment. EDS results reveal a compositional change in the vias, with a clear tendency of greater interaction between ions and the Ge atoms, as evidenced by greater compositional changes in the Ge rich films