5,360 research outputs found
PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model
In static timing analysis, clock-to-q delays of flip-flops are considered as
constants. Setup times and hold times are characterized separately and also
used as constants. The characterized delays, setup times and hold times, are
ap- plied in timing analysis independently to verify the perfor- mance of
circuits. In reality, however, clock-to-q delays of flip-flops depend on both
setup and hold times. Instead of being constants, these delays change with
respect to different setup/hold time combinations. Consequently, the simple ab-
straction of setup/hold times and constant clock-to-q delays introduces
inaccuracy in timing analysis. In this paper, we propose a holistic method to
consider the relation between clock-to-q delays and setup/hold time
combinations with a piecewise linear model. The result is more accurate than
that of traditional timing analysis, and the incorporation of the
interdependency between clock-to-q delays, setup times and hold times may also
improve circuit performance.Comment: IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
November 201
Throughput-driven floorplanning with wire pipelining
The size of future high-performance SoC is such that the time-of-flight of wires connecting distant pins in the layout can be much higher than the clock period. In order to keep the frequency as high as possible, the wires may be pipelined. However, the insertion of flip-flops may alter the throughput of the system due to the presence of loops in the logic netlist. In this paper, we address the problem of floorplanning a large design where long interconnects are pipelined by inserting the throughput in the cost function of a tool based on simulated annealing. The results obtained on a series of benchmarks are then validated using a simple router that breaks long interconnects by suitably placing flip-flops along the wires
EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers
At nanometer manufacturing technology nodes, process variations significantly
affect circuit performance. To combat them, post- silicon clock tuning buffers
can be deployed to balance timing bud- gets of critical paths for each
individual chip after manufacturing. The challenge of this method is that path
delays should be mea- sured for each chip to configure the tuning buffers
properly. Current methods for this delay measurement rely on path-wise
frequency stepping. This strategy, however, requires too much time from ex-
pensive testers. In this paper, we propose an efficient delay test framework
(EffiTest) to solve the post-silicon testing problem by aligning path delays
using the already-existing tuning buffers in the circuit. In addition, we only
test representative paths and the delays of other paths are estimated by
statistical delay prediction. Exper- imental results demonstrate that the
proposed method can reduce the number of frequency stepping iterations by more
than 94% with only a slight yield loss.Comment: ACM/IEEE Design Automation Conference (DAC), June 201
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Timing models for high-level synthesis
In this paper, we describe a timing model for clock estimation during high-level synthesis. In order to obtain realistic timing estimates, the proposed model considers all delay elements, including datapath, control and wire delays, and several technology factors, such as layout architecture, technology mapping, buffers insertion and loading effects. The experimental results show that this model can provide much better estimates than previous models. This model is well suited for automatic and interactive synthesis as well as feedback-driven synthesis where performance matrices must be rapidly and incrementally calculated
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