Coupling road vehicle aerodynamics and dynamics in simulation

A fully coupled system in which a vehicle s aerodynamic and handling responses can be simulated has been designed and evaluated using a severe crosswind test. Simulations of this type provide vehicle manufacturers with a useful alternative to on road tests, which are usually performed at a late stage in the development process with a proto- type vehicle. The proposed simulations could be performed much earlier and help to identify and resolve any aerodynamic sensitivities and safety concerns before significant resources are place in the design. It was shown that for the simulation of an artificial, on-track crosswind event, the use of the fully coupled system was unnecessary. A simplified, one-way coupled system, in which there is no feedback from the vehicle s dynamics to the aerodynamic simulation was sufficient in order to capture the vehicle s path deviation. The realistic properties of the vehicle and accurately calibrated driver model prevented any large attitude changes whilst immersed in the gust, from which variations to the aerodynamics could arise. It was suggested that this system may be more suited to other vehicle geometries more sensitive to yaw motions or applications where a high positional accuracy of the vehicle is required

At the Locus of Performance: A Case Study in Enhancing CPUs with Copious 3D-Stacked Cache

Over the last three decades, innovations in the memory subsystem were primarily targeted at overcoming the data movement bottleneck. In this paper, we focus on a specific market trend in memory technology: 3D-stacked memory and caches. We investigate the impact of extending the on-chip memory capabilities in future HPC-focused processors, particularly by 3D-stacked SRAM. First, we propose a method oblivious to the memory subsystem to gauge the upper-bound in performance improvements when data movement costs are eliminated. Then, using the gem5 simulator, we model two variants of LARC, a processor fabricated in 1.5 nm and enriched with high-capacity 3D-stacked cache. With a volume of experiments involving a board set of proxy-applications and benchmarks, we aim to reveal where HPC CPU performance could be circa 2028, and conclude an average boost of 9.77x for cache-sensitive HPC applications, on a per-chip basis. Additionally, we exhaustively document our methodological exploration to motivate HPC centers to drive their own technological agenda through enhanced co-design