Effects of annealing temperature and gas on pentacene OTFTs with HfLaO as gate dielectric

Pentacene organic thin-film transistors (OTFTs) with high-κ HfLaO as gate insulator were fabricated. HfLaO film was prepared by sputtering method. To improve the film quality, the dielectric was annealed in N 2, NH 3, or O 2 at two temperatures, i.e., 200 °C and 400 °C, respectively. The I-V characteristics of the OTFTs and C-V characteristics of corresponding organic capacitors were measured. The OTFTs could operate at a low operating voltage of below 5 V, and the dielectric constant of the HfLaO film could be above ten. For all the annealing gases, the OTFTs annealed at 400 °C achieved higher carrier mobility than their counterparts annealed at 200 °C (with the one annealed in NH 3 at 400 °C showing the highest carrier mobility of 0.45 cm 2/ V·s), which could be supported by SEM images which indicate that pentacene tended to form larger grains on HfLaO annealed at 400 °C than on that annealed at 200 °C. The C-V measurement of the organic capacitors indicated that the localized charge density in the organic semiconductor/oxide was lower for the 400 °C annealing than for the 200 °C annealing. Furthermore, through the characterization of gate current leakage, HfLaO film annealed at 400 °C achieved much smaller leakage than that annealed at 200 °C. Since the maximum processing temperature of ITO glass substrates is around 400 °C , this study shows that 400 °C is suitable for the annealing of HfLaO film in high-performance OTFTs on glass substrate. © 2011 IEEE.published_or_final_versio

High-performance Organic Thin-film Transistor

Organic compounds have been regarded as insulators for a long time. However, a semi-conductive organic material was discovered in the late 1940s. Since then, many organic semiconductors have been found and studied. However, the current carriers have quite lower mobility than those of inorganic counterparts so far. In spite of the low mobility, organic semiconductor devices have many interesting advantages such as low-cost fabrication, easy process, diverse substrate materials, and so on. Owing to the benefit of the low-cost fabrication, organic semiconductor can be applied to large-area electronic devices as well as ubiquitous devices. Although organic semiconductor has been widely utilized in electronics, its low performance has extremely restricted application in integrated circuits (ICs) that are essential for high-tech electronics. In order to be competitive in market, the performance improvement of organic thin film transistors (OTFTs) has become an indispensable prerequisite. Although the low performance of conventional OTFTs basically results from the inherent low carrier mobility, it is also attributed to low resolution fabrication processes and their inferior configuration with large parasitic capacitance. With regard to solutions to improve the performance of OTFTs, three novel strategies are proposed in this work: submicron metal patterning, self-aligned structure, and metal semiconductor field-effect transistor (MESFET)-like structure. To realize the solutions, a new concept of lithography, dual-layer thermal nanoimprint, is devised and its potential for submicron organic semiconductor patterning is experimented. In addition to the submicron resolution, two innovative patterning techniques, single-layer patterning and double-layer patterning, are successfully developed through the dual-layer thermal nanoimprint. Both patterning techniques can be utilized in fabricating self-aligned OTFTs and organic metal semiconductor field-effect transistors (OMESFETs). In the case of OMESFETs that require multiple-level metallization, the application of the dual-layer thermal nanoimprint lithography is extended from two-dimension to three-dimension to achieve self-aligned metallization that completely eliminates alignment errors. The 3D dual-layer thermal nanoimprint enables a sub-100 nm gap between metal patterns on an organic active layer. Because of the capability of nanoscale metal patterning on organic semiconductors with high overlay accuracy, this self-aligned metallization technique can be effectively utilized to fabricate high-performance top-contact OMESFETs

Morphology and performance in pentacene

Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.Includes bibliographical references (p. 57-60).by Ioannis Kymissis.M.Eng

Chemical Vapour Deposition of Large-area High-quality Graphene Films for Electronic Applications

Low Pressure Chemical Vapour Deposition (LPCVD) and transfer processes are explored and optimized to obtain large-area, continuous and high quality monolayer graphene on target substrate. The size of synthesized graphene reaches up to 20 mm * 20 mm, and can be further extended by upgrading to a larger reaction chamber; the monolayer coverage rate and conductivity is better than normal commercial graphene products on the market. A novel frame-assisted method is developed to transfer graphene without introducing many defects and impurities. Annealing and acetone treatment are combined to remove PMMA residues effectively and unharmfully. A new under-etching route to fabricate graphene free-standing structure is also proposed and explored. A novel non-contact microwave examination method has been employed to simplify the sheet resistance measurement processes and to avoid the effects of metallic contacts. This method is simple and non-destructive to graphene, and can be further integrated into the graphene production line in the future. A new double-layer device is fabricated and utilized to observe the microwave field effect in graphene. The interaction between graphene and oxygen under different temperatures and oxygen partial pressures is studied and discussed. Strontium Titanate films (SrTiO3 or STO) are deposited on transferred CVD grown graphene on MgO substrates. Based on the oxidation test result, the deposition process of Strontium Titanate is optimized to minimize the defects introduced on graphene. Raman mapping data show that graphene is still continuous after the STO deposition although the D band suggests some newly formed defects.Open Acces

Optik litografi ile organik alan etkili transistörlerin kanal aralığının hassas şekilde oluşturulması ve elde edilen cihazların elektriksel karakterizasyonu

06.03.2018 tarihli ve 30352 sayılı Resmi Gazetede yayımlanan “Yükseköğretim Kanunu İle Bazı Kanun Ve Kanun Hükmünde Kararnamelerde Değişiklik Yapılması Hakkında Kanun” ile 18.06.2018 tarihli “Lisansüstü Tezlerin Elektronik Ortamda Toplanması, Düzenlenmesi ve Erişime Açılmasına İlişkin Yönerge” gereğince tam metin erişime açılmıştır.Organik alan etkili transistör (OFET), üretim kolaylığı, düşük bütçeli yatırım ve esnek yüzeye uygulanabilmesi gibi avantajlarından dolayı, bilinen silisyum temelli transistörlerin pek çok uygulama alanında yerini almaya aday bir elektronik devre elemanıdır. OFET; bir alt tabaka üzerine önce iki iletken kontak (kaynak ve Savak) sonra üzerine yarıiletken polimer, bunun üzerine yalıtkan polimer ve en üste de kapı kontağı kaplanarak üretilir. Bu üretim sıralaması; kapının altta olması veya yarıiletken malzemenin kaynak ve Savak arasında olması gibi 4 farklı geometride de oluşturulabilmektedir. Elde edilen OFET'lerde Kaynak kapı arasına uygulanan gerilim ile kaynak Savak arasından geçen akım kontrol edilmektedir. Tez kapsamında öncelikle literatürde yer alan P tipi P3HT polimeri ile litografi yöntemi kullanılarak transistörler üretilmiş ve literatürde bulunan sonuçlarla karşılaştırılmıştır. Ticari bir polimer olan P3HT ile elde edilen transistörlerin karakteristik davranışları literatürde bulunan karakteristik davranışlarla son derece uyumlu çıkmıştır. Daha sonra özgün sentez bileşikler kullanılmıştır. Bu tezde, özgün malzemeler kullanılarak kapı/yalıtkan/kaynak Savak/yarıiletken yapılı yüksek performanslı OFET üretimi gerçekleştirilmiş ve sentezin özgün olmasının yanısıra performansın yüksek olması ile de literatüre büyük katkı sağlanmıştır. Yapılan çalışmada P3HT polimeri ile üretilen OFET'in kanal aralığına bağlı olarak eşik voltajı (VTh), açma kapama akım oranı(ION/IOFF), maksimum çıkış Savak akımı (IDS)max ve alan etkili mobilitesi µFET gibi transistör parametreleri incelenmiştir. Eşik voltajı küçük ve büyük kanal aralıklarında sapma gösterirken genelde -7 V civarında elde edilmiştir. ION/IOFF değeri, 6 µm için 1,01x103 olarak bulunurken 70 µm için 0,18x103 olarak elde edilmiş ve kanal aralığının artmasıyla azaldığı gözlenmiştir. (IDS)max değeri yine 6 µm için 4,24 µA bulunurken 70 µm için 0,34 µA olarak elde edilmiştir. Buradan kanal aralığının artmasıyla (IDS)max değerinin azaldığı anlaşılmaktadır. µFET değeri ise 6 µm için 2,1x10-3 cm2/Vs olarak bulunurken 70 µm için 6,3x10-3cm2/Vs olarak elde edilmiş ve kanal aralığıyla birlikte lineer olmayan bir artış gözlenmiştir. Yeni sentez malzeme ile üretilen OFET'in VTh, ION/IOFF, µFET ve geçiş iletkenliği (gm) değeri, sırasıyla 1,37 V, 0,7x103, 5,02 cm2/Vs ve 5,64 µS/mm olarak elde edilmiştir.Because of the advantages such as ease of production, low budget investment and applicability on flexible surfaces; organic field effect transistors ( OFET) are used as electronic circuit components that are candidate to take silicon based transistors' place in many applications. An OFET is fabricated by depositing two conducting contacts on substrate (source and drain) and then a semiconducting polymer on these contacts and later an insulating polymer on semiconducting polymer and lastly gate contact on insulating polymer. This fabrication order could be in four different geometry such as gate's being at the bottom or semiconductor materials being between source and drain. The voltage between source and gate, and the current passing through source and drain are controlled in fabricated OFET. Within the scope of dissertation, firstly transistors were fabricated by using P type P3HT polymer that is encountered in literature via lithography method and the results were compared with those in the literature. The performance of transistors fabricated with P3HT, which is a commercial polymer, has beeen found considerably compatible with the results of literature. Afterwards, novel synthesized compounds were used. In this dissertation, high performance OFET of gate/insulator/source drain/semiconductor structure were fabricated and considerable contribution was made to the literature through novel synthesized compounds and obtained high performance. In the study conducted, depending on channel length of OFET fabricated by P3HT polymer, transistor parameters such as threshold voltage (VTh), on off current ratio (ION/IOFF), maximum output drain current (IDS)max and field effect mobility (µFET) are investigated. Threshold voltage values are generally at about -7 V though there are deviations for small and large channel gaps. The value of ION/IOFF for 6 µm is 1,.01x103 whereas it is 0,18x103 for 70 µm, and it has been observed that it decreases with increasing the channel length. Similarly, value of (IDS)max for 6 µm is 4,24 µA whereas it is 0,34 µA for 70 µm, and it has been concluded that it decreases with increasing the channel length. As to the value of µFET, it is 2,1x10-3 cm2/Vs for 6 µm whereas it is 6,3x10-3 cm2/Vs for 70 µm, and it exhibits non linear increase with increasing the channel length. VTh, ION/IOFF, µFET and transconductance (gm) values of the OFET fabricated by newly synthesized compound are 1,37 V, 0,7x103, 5,02 cm2/Vs and 5,64 µS/mm, respectively