Cubing Units Using Carry-Save Array Implementations

This study is aimed at designing a specialized functional unit to perform the operation of Cubing. The design has been implemented based on the concept of carry-save array multipliers. The carry save concept aims at accelerating the process of addition by delaying the carry propagation operation till the last step. The motivation behind using array structures is simple. Array structures are regular and easy to design. This paper first looks at a simple cubing unit that can accept only unsigned inputs. This design is then modified based on mathematical derivations and architecture for signed cubing unit or two's complement cubing unit is derived. The designs have been tested, synthesized and compared with the traditional multiplication techniques for area and delay. When the different designs for various bit sizes of operands were tested and synthesized, some really interesting results were arrived at. The algorithmic analysis showed that the cubing unit implementation would require more delay and area as compared to two passes for the same operation through corresponding traditional CSAMs. After synthesis, while the results agreed with the area requirement, for the 6-bit version, it was seen that the cubing design is actually faster as compared to the traditional implementation. The interesting thing about the cubing unit design is that its area requirement and delay increases almost exponentially with the length of the input operands. Careful floorplanning and layout techniques must be employed in order to arrive at a good design.School of Electrical & Computer Engineerin

Adaptive and hybrid schemes for efficient parallel squaring and cubing units

Squaring (X2) and cubing (X3) units are special operations of multiplication used in many applications, such as image compression, equalization, decoding and demodulation, 3D graphics, scientific computing, artificial neural networks, logarithmic number system, and multimedia application. They can also be an efficient way to compute other basic functions. Therefore, improving their performances is a goal for many researchers. This dissertation will discuss modification to algorithms to compute parallel squaring and cubing units in both signed and unsigned representation. After that, truncated technique is applied to improve their performance. Each unit is modeled and estimated to obtain its area, delay by using linear evaluation model. A C program was written to generate Hardware Description Language files for each unit. These units are simulated and verified in simulation. Moreover, area, delay, and power consumption are calculated for each unit and compared with those ones in previous approaches for both Virtex 5 Xilinx FPGA and IBM 65nm ASIC technologies