VLSI layout generation of a programmable CRC chip

VLSI layout generation of a programmable CRC chip with a CRC of 16-bits is presented. The hardware of CRC generator is specified in a hardware description language (HDL). The hardware compiler and functional level simulator of HDL are used for logic synthesis. The second stage of the compilation process generates a net list of logic gates. The net list so produced is translated to RNL compatible net list by a translator program. The layout subsystem of VPNR is used to generate the VLSI layout of the programmable CRC chip from RNL netlist. The design rules and technology files of MOSIS are used. The layout is viewed in the MAGIC layout editor and simulated by irsim at the transistor-level. The CRC chip can be used in a number of applications. These include areas such as data communications for error detection and correction, digital system testing for test pattern generation and signature analysis, and mass storage devices for parallel information transfer

Design and Simulation of Parallel CRC Generation Architecture for High Speed Application

ABSTRACT: High speed data transmission is the current scenario in networking environment. Cyclic redundancy check (CRC) is essential method for detecting error when the data is transmitted. With challenging the speed of transmitting data, to synchronize with speed, it's necessary to increase speed of CRC generation. Starting from the serial architecture identified a recursive formula from which parallel design is derived. For simulation and functional verification we will use ModelSim and AlteraQuartus 2. A cyclic redundancy check (CRC) is an error detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This paper is based on pipelined CRC method is designed to achieve high throughput by cascading buffers, which improves the time further

VLSI LAYOUT GENERATION OF A PROGRAMMABLE CRC CHIP

VLSI layout generation of a programable CRC chip with a CRC of 16-bits is presented. The hardware of CRC generator is specified in a hardware description language (HDL). The hardware compiler and functional level simulator of HDL are used for logic synthesis. the second stage of the compilation process generates a netlist of logic gates. The netlist so produced is translated to RNL compatible netlist by a translator program. The layout subsystem of VPNR is used to generate the VLSI layout sub-system of VPNR is used to generate the VLSI layout of the programmable CRC chip from the RNL netlist. The design rules and technology files of MOSIS are used. The layout is viewed in MAGIC layout editor and simulated by irsim at transistor level. The CRC chip can be used in a number applications. These include areas such as data communication for error detection and correction, digital system testing for test pattern generation and signature analysis, and mass storage devices for parallel information transfers

Implementation of a station/network interface for a CAMB tree network

Packet collisions and their resolution create a performance bottleneck in random-access LANs. A hardware solution to this problem is to use collision avoidance switches. These switches allow the implementation of random access protocols without the penalty of collisions among packets. An architecture based on collision avoidance is the CAMB (Collision Avoidance Multiple Broadcast) tree network, where concurrent broadcasts are possible.This paper is a companion to an earlier report. "TTL Implementations of a CAMB Tree Switch," where a tree network architecture was described for two different implementations of a CAMB tree switch. In the pages that follow, a hardware implementation of the interface between the network stations and the packet switches is proposed. This implementation is based on the first switch design in the companion paper

On the Decoding of Polar Codes on Permuted Factor Graphs

Polar codes are a channel coding scheme for the next generation of wireless communications standard (5G). The belief propagation (BP) decoder allows for parallel decoding of polar codes, making it suitable for high throughput applications. However, the error-correction performance of polar codes under BP decoding is far from the requirements of 5G. It has been shown that the error-correction performance of BP can be improved if the decoding is performed on multiple permuted factor graphs of polar codes. However, a different BP decoding scheduling is required for each factor graph permutation which results in the design of a different decoder for each permutation. Moreover, the selection of the different factor graph permutations is at random, which prevents the decoder to achieve a desirable error-correction performance with a small number of permutations. In this paper, we first show that the permutations on the factor graph can be mapped into suitable permutations on the codeword positions. As a result, we can make use of a single decoder for all the permutations. In addition, we introduce a method to construct a set of predetermined permutations which can provide the correct codeword if the decoding fails on the original permutation. We show that for the 5G polar code of length $1024$, the error-correction performance of the proposed decoder is more than $0.25$ dB better than that of the BP decoder with the same number of random permutations at the frame error rate of $10^{-4}$

Cryptanalysis of two mutual authentication protocols for low-cost RFID

Radio Frequency Identification (RFID) is appearing as a favorite technology for automated identification, which can be widely applied to many applications such as e-passport, supply chain management and ticketing. However, researchers have found many security and privacy problems along RFID technology. In recent years, many researchers are interested in RFID authentication protocols and their security flaws. In this paper, we analyze two of the newest RFID authentication protocols which proposed by Fu et al. and Li et al. from several security viewpoints. We present different attacks such as desynchronization attack and privacy analysis over these protocols.Comment: 17 pages, 2 figures, 1 table, International Journal of Distributed and Parallel system